riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

fixes to match verilog X semantics

Browse Source
This commit is contained in:
Yunsup Lee 2012-03-19 03:08:53 -07:00
parent bd27d0fab2
commit 264732556f
3 changed files with 17 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
rocket/src/main/scala/ctrl.scala
View File

@ -333,7 +333,7 @@ class rocketCtrl extends Component
val id_waddr = Mux(id_sel_wa === WA_RA, RA, io.dpath.inst(31,27));
val wb_reg_div_mul_val = Reg(resetVal = Bool(false))
val wb_reg_dcache_miss = Reg(io.dmem.resp_miss, resetVal = Bool(false));
val wb_reg_dcache_miss = Reg(io.dmem.resp_miss || io.dmem.resp_nack, resetVal = Bool(false));
val id_reg_valid = Reg(resetVal = Bool(false));
val id_reg_btb_hit = Reg(resetVal = Bool(false));
@ -529,15 +529,15 @@ class rocketCtrl extends Component
val bge = ~io.dpath.br_lt;
val bgeu = ~io.dpath.br_ltu;
val br_taken =
(ex_reg_br_type === BR_EQ) & beq |
(ex_reg_br_type === BR_NE) & bne |
(ex_reg_br_type === BR_LT) & blt |
(ex_reg_br_type === BR_LTU) & bltu |
(ex_reg_br_type === BR_GE) & bge |
(ex_reg_br_type === BR_GEU) & bgeu |
(ex_reg_br_type === BR_J); // treat J/JAL like taken branches
val jr_taken = ex_reg_br_type === BR_JR
val br_taken = !(wb_reg_dcache_miss && ex_reg_load_use) &&
((ex_reg_br_type === BR_EQ) && beq ||
(ex_reg_br_type === BR_NE) && bne ||
(ex_reg_br_type === BR_LT) && blt ||
(ex_reg_br_type === BR_LTU) && bltu ||
(ex_reg_br_type === BR_GE) && bge ||
(ex_reg_br_type === BR_GEU) && bgeu ||
(ex_reg_br_type === BR_J)) // treat J/JAL like taken branches
val jr_taken = !(wb_reg_dcache_miss && ex_reg_load_use) && ex_reg_br_type === BR_JR
val mem_reg_div_mul_val = Reg(){Bool()};
val mem_reg_eret = Reg(){Bool()};

11
rocket/src/main/scala/ctrl_util.scala
View File

@ -20,13 +20,14 @@ class rocketCtrlSboard(entries: Int, nread: Int, nwrite: Int) extends Component
val w = Vec(nwrite) { new write_port() }
}
val busybits = Reg(resetVal = Bits(0, entries));
val busybits = Vec(entries) { Reg(resetVal = Bool(false)) }
for (i <- 0 until nread)
io.r(i).data := busybits(io.r(i).addr)
var wdata = busybits
for (i <- 0 until nwrite)
wdata = wdata.bitSet(io.w(i).addr, Mux(io.w(i).en, io.w(i).data, wdata(io.w(i).addr)))
busybits := wdata
for (i <- 0 until nwrite) {
when (io.w(i).en) {
busybits(io.w(i).addr) := io.w(i).data
}
}
}

2
rocket/src/main/scala/nbdcache.scala
View File

@ -401,7 +401,7 @@ class MSHRFile extends Component {
val (replay_read, replay_write) = cpuCmdToRW(replay.bits.cmd)
val sdq_free = replay.valid && replay.ready && replay_write
sdq_val := sdq_val & ~(sdq_free.toUFix << replay.bits.sdq_id) |
sdq_val := sdq_val & ~((UFix(1) << replay.bits.sdq_id) & Fill(sdq_free, NSDQ)) |
PriorityEncoderOH(~sdq_val(NSDQ-1,0)) & Fill(NSDQ, sdq_enq && io.req.bits.tag_miss)
io.data_req.bits.data := sdq.read(Mux(replay.valid && !replay.ready, replay.bits.sdq_id, replay_arb.io.out.bits.sdq_id))