riscv/rocket-chip
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fixes to match verilog X semantics

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This commit is contained in:
Yunsup Lee
2012-03-19 03:08:53 -07:00
parent bd27d0fab2
commit 264732556f
3 changed files with 17 additions and 16 deletions
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2
rocket/src/main/scala/nbdcache.scala
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@ -401,7 +401,7 @@ class MSHRFile extends Component {
val (replay_read, replay_write) = cpuCmdToRW(replay.bits.cmd)
val sdq_free = replay.valid && replay.ready && replay_write
sdq_val := sdq_val & ~(sdq_free.toUFix << replay.bits.sdq_id) |
sdq_val := sdq_val & ~((UFix(1) << replay.bits.sdq_id) & Fill(sdq_free, NSDQ)) |
PriorityEncoderOH(~sdq_val(NSDQ-1,0)) & Fill(NSDQ, sdq_enq && io.req.bits.tag_miss)
io.data_req.bits.data := sdq.read(Mux(replay.valid && !replay.ready, replay.bits.sdq_id, replay_arb.io.out.bits.sdq_id))