riscv/rocket-chip
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debug: fix some typos related to the ID->SEL mapping functions

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Megan Wachs 2017-04-04 13:43:39 -07:00 committed by Andrew Waterman
parent b94f1f15b0
commit 2601740542
1 changed files with 9 additions and 9 deletions
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18
src/main/scala/uncore/devices/debug/Debug.scala
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@ -123,7 +123,7 @@ case class DebugModuleConfig (
nSerialPorts : Int, nSerialPorts : Int,
supportQuickAccess : Boolean, supportQuickAccess : Boolean,
supportHartArray : Boolean, supportHartArray : Boolean,
hartidToHartSel : (UInt) => UInt, hartIdToHartSel : (UInt) => UInt,
hartSelToHartId : (UInt) => UInt hartSelToHartId : (UInt) => UInt
) { ) {
@ -698,11 +698,11 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
haltedBitRegs(component) := false.B haltedBitRegs(component) := false.B
}.otherwise { }.otherwise {
when (hartHaltedWrEn) { when (hartHaltedWrEn) {
when (hartIdToHartSel(hartHaltedId) === component.U) { when (cfg.hartIdToHartSel(hartHaltedId) === component.U) {
haltedBitRegs(component) := true.B haltedBitRegs(component) := true.B
} }
}.elsewhen (hartResumingWrEn) { }.elsewhen (hartResumingWrEn) {
when (hartIdToHartSel(hartResumingId) === component.U) { when (cfg.hartIdToHartSel(hartResumingId) === component.U) {
haltedBitRegs(component) := false.B haltedBitRegs(component) := false.B
} }
} }
@ -777,9 +777,9 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
} }
val goBytes = Wire(init = Vec.fill(1024){0.U(8.W)}) val goBytes = Wire(init = Vec.fill(1024){0.U(8.W)})
goBytes(hartSelToHartId(selectedHartReg)) := Cat(0.U(7.W), goReg) assert ((cfg.hartSelToHartId(selectedHartReg) < 1024.U),
assert ((hartSelToHartId(selectedHartReg) < 1024), "HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < 1024 for it to work.");
"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < 1024 for it to work"); goBytes(cfg.hartSelToHartId(selectedHartReg)) := Cat(0.U(7.W), goReg)
//---------------------------- //----------------------------
// Abstract Command Decoding & Generation // Abstract Command Decoding & Generation
@ -980,7 +980,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
// We can't just look at 'hartHalted' here, because // We can't just look at 'hartHalted' here, because
// hartHaltedWrEn is overloaded to mean 'got an ebreak' // hartHaltedWrEn is overloaded to mean 'got an ebreak'
// which may have happened when we were already halted. // which may have happened when we were already halted.
when(goReg === false.B && hartHaltedWrEn && (hartIdToHartSel(hartHaltedId) === selectedHartReg)){ when(goReg === false.B && hartHaltedWrEn && (cfg.hartIdToHartSel(hartHaltedId) === selectedHartReg)){
ctrlStateNxt := CtrlState(Abstract) ctrlStateNxt := CtrlState(Abstract)
goAbstract := true.B goAbstract := true.B
} }
@ -994,7 +994,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
// We can't just look at 'hartHalted' here, because // We can't just look at 'hartHalted' here, because
// hartHaltedWrEn is overloaded to mean 'got an ebreak' // hartHaltedWrEn is overloaded to mean 'got an ebreak'
// which may have happened when we were already halted. // which may have happened when we were already halted.
when(goReg === false.B && hartHaltedWrEn && (hartIdToHartSel(hartHaltedId) === selectedHartReg)){ when(goReg === false.B && hartHaltedWrEn && (cfg.hartIdToHartSel(hartHaltedId) === selectedHartReg)){
when (accessRegisterCommandReg.postexec) { when (accessRegisterCommandReg.postexec) {
ctrlStateNxt := CtrlState(PostExec) ctrlStateNxt := CtrlState(PostExec)
goProgramBuffer := true.B goProgramBuffer := true.B
@ -1012,7 +1012,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
// We can't just look at 'hartHalted' here, because // We can't just look at 'hartHalted' here, because
// hartHaltedWrEn is overloaded to mean 'got an ebreak' // hartHaltedWrEn is overloaded to mean 'got an ebreak'
// which may have happened when we were already halted. // which may have happened when we were already halted.
when(goReg === false.B && hartHaltedWrEn && (hartIdToHartSel(hartHaltedId) === selectedHartReg)){ when(goReg === false.B && hartHaltedWrEn && (cfg.hartIdToHartSel(hartHaltedId) === selectedHartReg)){
ctrlStateNxt := CtrlState(Waiting) ctrlStateNxt := CtrlState(Waiting)
} }
when(hartExceptionWrEn) { when(hartExceptionWrEn) {