riscv/rocket-chip
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Don't implicitly create Vecs, since they're heavyweight

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This commit is contained in:
Andrew Waterman
2016-07-06 01:31:56 -07:00
parent 8bd7e3932b
commit 25fdabdd59
7 changed files with 28 additions and 13 deletions
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2
rocket/src/main/scala/tile.scala
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@ -105,7 +105,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))
if (p(RoccNCSRs) > 0) {
core.io.rocc.csr.rdata <> roccs.map(_.io.csr.rdata).reduce(_ ++ _)
core.io.rocc.csr.rdata <> roccs.flatMap(_.io.csr.rdata)
for ((rocc, accelParams) <- roccs.zip(buildRocc)) {
rocc.io.csr.waddr := core.io.rocc.csr.waddr
rocc.io.csr.wdata := core.io.rocc.csr.wdata