riscv/rocket-chip
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Don't implicitly create Vecs, since they're heavyweight

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Andrew Waterman committed 2016-07-06 01:41:31 -07:00
1 parent 8bd7e3932b
commit 25fdabdd59
7 files changed
+28 -13
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rocket/src/main/scala/dcache.scala
+1 -1
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@@ -116,7 +116,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val s1_paddr = Cat(tlb.io.resp.ppn, s1_req.addr(pgIdxBits-1,0))
val s1_tag = Mux(s1_probe, probe_bits.addr_block >> idxBits, s1_paddr(paddrBits-1, untagBits))
val s1_hit_way = Cat(meta.io.resp.map(r => r.coh.isValid() && r.tag === s1_tag).reverse)
val s1_hit_way = meta.io.resp.map(r => r.coh.isValid() && r.tag === s1_tag).toBits
val s1_hit_state = ClientMetadata.onReset.fromBits(
meta.io.resp.map(r => Mux(r.tag === s1_tag, r.coh.toBits, UInt(0)))
.reduce (_|_))