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Remove unused signal from TLB interface

This commit is contained in:
Andrew Waterman 2017-06-08 11:21:44 -07:00
parent d5f80df0ae
commit 25f585f2a9
4 changed files with 0 additions and 4 deletions

View File

@ -127,7 +127,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
tlb.io.req.bits.passthrough := s1_req.phys
tlb.io.req.bits.vaddr := s1_req.addr
tlb.io.req.bits.instruction := false
tlb.io.req.bits.store := s1_write
tlb.io.req.bits.size := s1_req.typ
tlb.io.req.bits.cmd := s1_req.cmd
when (!tlb.io.req.ready && !io.cpu.req.bits.phys) { io.cpu.req.ready := false }

View File

@ -145,7 +145,6 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
tlb.io.req.bits.vaddr := s1_pc
tlb.io.req.bits.passthrough := Bool(false)
tlb.io.req.bits.instruction := Bool(true)
tlb.io.req.bits.store := Bool(false)
tlb.io.req.bits.sfence := io.cpu.sfence
tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth)

View File

@ -712,7 +712,6 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
dtlb.io.req.bits.passthrough := s1_req.phys
dtlb.io.req.bits.vaddr := s1_req.addr
dtlb.io.req.bits.instruction := Bool(false)
dtlb.io.req.bits.store := s1_write
dtlb.io.req.bits.size := s1_req.typ
dtlb.io.req.bits.cmd := s1_req.cmd
when (!dtlb.io.req.ready && !io.cpu.req.bits.phys) { io.cpu.req.ready := Bool(false) }

View File

@ -27,7 +27,6 @@ class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) {
val vaddr = UInt(width = vaddrBitsExtended)
val passthrough = Bool()
val instruction = Bool()
val store = Bool()
val sfence = Valid(new SFenceReq)
val size = UInt(width = log2Ceil(lgMaxSize + 1))
val cmd = Bits(width = M_SZ)