riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink: AtomicAutomata should OR the Get error with the Put error

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-11-06 11:31:23 -08:00
parent dcf67b49fa
commit 25ea7fa852
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/tilelink/AtomicAutomata.scala
View File

@ -188,6 +188,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source) val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source)
val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b } val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b }
val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data)) val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data))
val d_cam_error = Mux1H(d_cam_sel_match, cam_d.map(_.error))
val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) Bool(false) else val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) Bool(false) else
out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported
val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) } val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) }
@ -199,6 +200,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
(d_cam_sel zip cam_d) foreach { case (en, r) => (d_cam_sel zip cam_d) foreach { case (en, r) =>
when (en && d_ackd) { when (en && d_ackd) {
r.data := out.d.bits.data r.data := out.d.bits.data
r.error := out.d.bits.error
} }
} }
(d_cam_sel zip cam_s) foreach { case (en, r) => (d_cam_sel zip cam_s) foreach { case (en, r) =>
@ -219,6 +221,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
when (d_replace) { // minimal muxes when (d_replace) { // minimal muxes
in.d.bits.opcode := TLMessages.AccessAckData in.d.bits.opcode := TLMessages.AccessAckData
in.d.bits.data := d_cam_data in.d.bits.data := d_cam_data
in.d.bits.error := d_cam_error || out.d.bits.error
} }
} else { } else {
out.a.valid := in.a.valid out.a.valid := in.a.valid
@ -270,7 +273,8 @@ object TLAtomicAutomata
val lut = UInt(width = 4) val lut = UInt(width = 4)
} }
class CAM_D(params: CAMParams) extends GenericParameterizedBundle(params) { class CAM_D(params: CAMParams) extends GenericParameterizedBundle(params) {
val data = UInt(width = params.a.dataBits) val data = UInt(width = params.a.dataBits)
val error = Bool()
} }
} }