diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index dcffc636..f60278f8 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -572,6 +572,8 @@ class rocketCtrl extends Component
                    io.fpu.dec.wen  && fp_sboard.io.r(3).data
   } 
 
+  var vec_replay = Bool(false)
+
   if (HAVE_VEC)
   {
     // vector control
@@ -579,6 +581,7 @@ class rocketCtrl extends Component
 
     io.vec_dpath <> vec.io.dpath
     io.vec_iface <> vec.io.iface
+    vec_replay = vec.io.replay
 
     vec.io.sr_ev := io.dpath.status(SR_EV)
   }
@@ -655,7 +658,7 @@ class rocketCtrl extends Component
   mem_reg_replay := replay_ex && !take_pc_wb;
   mem_reg_kill := kill_ex;
 
-  wb_reg_replay       := replay_mem && !take_pc_wb;
+  wb_reg_replay       := replay_mem && !take_pc_wb || vec_replay;
   wb_reg_exception    := mem_exception && !take_pc_wb;
   wb_reg_cause        := mem_cause;
 
diff --git a/rocket/src/main/scala/ctrl_vec.scala b/rocket/src/main/scala/ctrl_vec.scala
index 4fe44eb5..2c2897d8 100644
--- a/rocket/src/main/scala/ctrl_vec.scala
+++ b/rocket/src/main/scala/ctrl_vec.scala
@@ -31,6 +31,7 @@ class ioCtrlVec extends Bundle
   val dpath = new ioCtrlDpathVec()
   val iface = new ioCtrlVecInterface()
   val sr_ev = Bool(INPUT)
+  val replay = Bool(OUTPUT)
 }
 
 class rocketCtrlVec extends Component
@@ -88,16 +89,26 @@ class rocketCtrlVec extends Component
   ))
 
   val wb_vec_val :: wb_sel_vcmd :: wb_sel_vimm :: wb_vec_wen :: wb_vec_fn :: wb_vec_appvlmask :: veccs0 = veccs
-  val wb_vec_cmdq_val :: wb_vec_ximm1q_val :: wb_vec_ximm2q_val :: Nil = veccs0
+  val wb_vec_cmdq_enq :: wb_vec_ximm1q_enq :: wb_vec_ximm2q_enq :: Nil = veccs0
 
   val valid_common = io.dpath.valid && io.sr_ev && wb_vec_val.toBool && !(wb_vec_appvlmask.toBool && io.dpath.appvl0)
 
-  io.iface.vcmdq_valid := valid_common && wb_vec_cmdq_val
-  io.iface.vximm1q_valid := valid_common && wb_vec_ximm1q_val
-  io.iface.vximm2q_valid := valid_common && wb_vec_ximm2q_val
+  val mask_wb_vec_cmdq_ready = !wb_vec_cmdq_enq || io.iface.vcmdq_ready
+  val mask_wb_vec_ximm1q_ready = !wb_vec_ximm1q_enq || io.iface.vximm1q_ready
+  val mask_wb_vec_ximm2q_ready = !wb_vec_ximm2q_enq || io.iface.vximm2q_ready
 
   io.dpath.wen := wb_vec_wen.toBool
   io.dpath.fn := wb_vec_fn
   io.dpath.sel_vcmd := wb_sel_vcmd
   io.dpath.sel_vimm := wb_sel_vimm
+
+  io.iface.vcmdq_valid := valid_common && wb_vec_cmdq_enq && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready
+  io.iface.vximm1q_valid := valid_common && mask_wb_vec_cmdq_ready && wb_vec_ximm1q_enq && mask_wb_vec_ximm2q_ready
+  io.iface.vximm2q_valid := valid_common && mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && wb_vec_ximm2q_enq
+
+  io.replay := valid_common && (
+    wb_vec_cmdq_enq && !io.iface.vcmdq_ready ||
+    wb_vec_ximm1q_enq && !io.iface.vximm1q_ready ||
+    wb_vec_ximm2q_enq && !io.iface.vximm2q_ready
+  )
 }