riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

coreplex: re-enable stateless L2 config

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-01-19 13:51:50 -08:00
parent 4bdb2e5d68
commit 258abc5629
1 changed files with 5 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/main/scala/coreplex/Configs.scala
View File

@ -143,12 +143,11 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
* DO NOT use this configuration.
*/
class WithStatelessBridge extends Config((site, here, up) => {
/* !!! FIXME
case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (_, _) =>
val pass = LazyModule(new TLBuffer(0)(site))
(pass.node, pass.node)
case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case q =>
implicit val p = q
val cork = LazyModule(new TLCacheCork(unsafe = true))
(cork.node, TLWidthWidget(p(L1toL2Config).beatBytes)(cork.node))
})
*/
case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
})