riscv/rocket-chip
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Optionally prefetch next I$ line into L2$ on miss

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This commit is contained in:
Andrew Waterman
2017-08-02 17:10:35 -07:00
parent 744cdb2f72
commit 2537d0d54e
2 changed files with 44 additions and 8 deletions
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src/main/scala/rocket/Frontend.scala
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@ -141,6 +141,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
icache.io.s2_vaddr := s2_pc
icache.io.s1_kill := s2_redirect || tlb.io.resp.miss || s2_replay
icache.io.s2_kill := s2_speculative && !s2_tlb_resp.cacheable || s2_xcpt
icache.io.s2_prefetch := s2_tlb_resp.prefetchable
fq.io.enq.valid := s2_valid && (icache.io.resp.valid || !s2_tlb_resp.miss && icache.io.s2_kill)
fq.io.enq.bits.pc := s2_pc