riscv/rocket-chip
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fix broadcast hub and TL -> NASTI converter to support subblock operations

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Howard Mao committed 2015-09-14 12:56:44 -07:00
1 parent 24389a5257
commit 24f3fac90a
3 files changed
+102 -44
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uncore/src/main/scala/uncore.scala
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@@ -20,6 +20,7 @@ trait CoherenceAgentParameters extends UsesParameters {
val innerTLParams = params.alterPartial({case TLId => params(InnerTLId)})
val innerDataBeats = innerTLParams(TLDataBeats)
val innerDataBits = innerTLParams(TLDataBits)
val innerWriteMaskBits = innerTLParams(TLWriteMaskBits)
val innerBeatAddrBits = log2Up(innerDataBeats)
val innerByteAddrBits = log2Up(innerDataBits/8)
require(outerDataBeats == innerDataBeats) //TODO: must fix all xact_data Vecs to remove this requirement