1
0

rocketchip: pass variable l1tol2 connections into coreplex

This commit is contained in:
Wesley W. Terpstra 2017-01-29 11:16:00 -08:00
parent d5fa159063
commit 24ee7f45f5
5 changed files with 16 additions and 41 deletions

View File

@ -11,17 +11,14 @@ import util._
class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex
with CoreplexRISCVPlatform with CoreplexRISCVPlatform
with HasL2MasterPort
with HasRocketTiles { with HasRocketTiles {
override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this)) override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this))
} }
class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
with CoreplexRISCVPlatformBundle with CoreplexRISCVPlatformBundle
with HasL2MasterPortBundle
with HasRocketTilesBundle with HasRocketTilesBundle
class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
with CoreplexRISCVPlatformModule with CoreplexRISCVPlatformModule
with HasL2MasterPortModule
with HasRocketTilesModule with HasRocketTilesModule

View File

@ -24,9 +24,13 @@ trait CoreplexNetwork extends HasCoreplexParameters {
val mmio = TLOutputNode() val mmio = TLOutputNode()
val mmioInt = IntInputNode() val mmioInt = IntInputNode()
val l2in = TLInputNode()
intBar.intnode := mmioInt intBar.intnode := mmioInt
// Allows a variable number of inputs from outside to the Xbar
l1tol2.node :=* l2in
cbus.node := cbus.node :=
TLBuffer()( TLBuffer()(
TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
@ -43,6 +47,7 @@ trait CoreplexNetworkBundle extends HasCoreplexParameters {
val mmio = outer.mmio.bundleOut val mmio = outer.mmio.bundleOut
val interrupts = outer.mmioInt.bundleIn val interrupts = outer.mmioInt.bundleIn
val l2in = outer.l2in.bundleIn
} }
trait CoreplexNetworkModule extends HasCoreplexParameters { trait CoreplexNetworkModule extends HasCoreplexParameters {
@ -93,21 +98,3 @@ trait BankedL2CoherenceManagersModule extends CoreplexNetworkModule {
val outer: BankedL2CoherenceManagers val outer: BankedL2CoherenceManagers
val io: BankedL2CoherenceManagersBundle val io: BankedL2CoherenceManagersBundle
} }
/////
trait HasL2MasterPort extends CoreplexNetwork {
val module: HasL2MasterPortModule
val l2in = TLInputNode()
l1tol2.node := TLBuffer()(l2in)
}
trait HasL2MasterPortBundle extends CoreplexNetworkBundle {
val outer: HasL2MasterPort
val l2in = outer.l2in.bundleIn
}
trait HasL2MasterPortModule extends CoreplexNetworkModule {
val outer: HasL2MasterPort
val io: HasL2MasterPortBundle
}

View File

@ -34,6 +34,7 @@ trait TopNetwork extends HasPeripheryParameters {
val socBus = LazyModule(new TLXbar) val socBus = LazyModule(new TLXbar)
val peripheryBus = LazyModule(new TLXbar) val peripheryBus = LazyModule(new TLXbar)
val intBus = LazyModule(new IntXbar) val intBus = LazyModule(new IntXbar)
val l2 = LazyModule(new TLBuffer)
peripheryBus.node := peripheryBus.node :=
TLBuffer()( TLBuffer()(
@ -62,13 +63,3 @@ class BaseTopBundle[+L <: BaseTop](_outer: L) extends BareTopBundle(_outer)
class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io) class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io)
with TopNetworkModule with TopNetworkModule
trait L2Crossbar extends TopNetwork {
val l2 = LazyModule(new TLXbar)
}
trait L2CrossbarBundle extends TopNetworkBundle {
}
trait L2CrossbarModule extends TopNetworkModule {
}

View File

@ -165,7 +165,7 @@ trait PeripheryMasterAXI4MMIOModule {
///// /////
// PeripherySlaveAXI4 is an example, make your own cake pattern like this one. // PeripherySlaveAXI4 is an example, make your own cake pattern like this one.
trait PeripherySlaveAXI4 extends L2Crossbar { trait PeripherySlaveAXI4 extends TopNetwork {
private val config = p(ExtIn) private val config = p(ExtIn)
val l2_axi4 = AXI4BlindInputNode(Seq(AXI4MasterPortParameters( val l2_axi4 = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
masters = Seq(AXI4MasterParameters( masters = Seq(AXI4MasterParameters(
@ -179,12 +179,12 @@ trait PeripherySlaveAXI4 extends L2Crossbar {
l2_axi4)))) l2_axi4))))
} }
trait PeripherySlaveAXI4Bundle extends L2CrossbarBundle { trait PeripherySlaveAXI4Bundle extends TopNetworkBundle {
val outer: PeripherySlaveAXI4 val outer: PeripherySlaveAXI4
val l2_axi4 = outer.l2_axi4.bundleIn val l2_axi4 = outer.l2_axi4.bundleIn
} }
trait PeripherySlaveAXI4Module extends L2CrossbarModule { trait PeripherySlaveAXI4Module extends TopNetworkModule {
val outer: PeripherySlaveAXI4 val outer: PeripherySlaveAXI4
val io: PeripherySlaveAXI4Bundle val io: PeripherySlaveAXI4Bundle
// nothing to do // nothing to do
@ -231,7 +231,7 @@ trait PeripheryMasterTLMMIOModule {
///// /////
// NOTE: this port is NOT allowed to issue Acquires // NOTE: this port is NOT allowed to issue Acquires
trait PeripherySlaveTL extends L2Crossbar { trait PeripherySlaveTL extends TopNetwork {
private val config = p(ExtIn) private val config = p(ExtIn)
val l2_tl = TLBlindInputNode(Seq(TLClientPortParameters( val l2_tl = TLBlindInputNode(Seq(TLClientPortParameters(
clients = Seq(TLClientParameters( clients = Seq(TLClientParameters(
@ -243,12 +243,12 @@ trait PeripherySlaveTL extends L2Crossbar {
l2_tl)) l2_tl))
} }
trait PeripherySlaveTLBundle extends L2CrossbarBundle { trait PeripherySlaveTLBundle extends TopNetworkBundle {
val outer: PeripherySlaveTL val outer: PeripherySlaveTL
val l2_tl = outer.l2_tl.bundleIn val l2_tl = outer.l2_tl.bundleIn
} }
trait PeripherySlaveTLModule extends L2CrossbarModule { trait PeripherySlaveTLModule extends TopNetworkModule {
val outer: PeripherySlaveTL val outer: PeripherySlaveTL
val io: PeripherySlaveTLBundle val io: PeripherySlaveTLBundle
// nothing to do // nothing to do

View File

@ -10,23 +10,23 @@ import uncore.devices._
import util._ import util._
import coreplex._ import coreplex._
trait RocketPlexMaster extends L2Crossbar { trait RocketPlexMaster extends TopNetwork {
val module: RocketPlexMasterModule val module: RocketPlexMasterModule
val mem: Seq[TLInwardNode] val mem: Seq[TLInwardNode]
val coreplex = LazyModule(new DefaultCoreplex) val coreplex = LazyModule(new DefaultCoreplex)
coreplex.l2in := l2.node coreplex.l2in :=* l2.node
socBus.node := coreplex.mmio socBus.node := coreplex.mmio
coreplex.mmioInt := intBus.intnode coreplex.mmioInt := intBus.intnode
mem.foreach { _ := coreplex.mem } mem.foreach { _ := coreplex.mem }
} }
trait RocketPlexMasterBundle extends L2CrossbarBundle { trait RocketPlexMasterBundle extends TopNetworkBundle {
val outer: RocketPlexMaster val outer: RocketPlexMaster
} }
trait RocketPlexMasterModule extends L2CrossbarModule { trait RocketPlexMasterModule extends TopNetworkModule {
val outer: RocketPlexMaster val outer: RocketPlexMaster
val io: RocketPlexMasterBundle val io: RocketPlexMasterBundle
val clock: Clock val clock: Clock