riscv/rocket-chip
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rocketchip: pass variable l1tol2 connections into coreplex

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This commit is contained in:
Wesley W. Terpstra
2017-01-29 11:16:00 -08:00
parent d5fa159063
commit 24ee7f45f5
5 changed files with 16 additions and 41 deletions
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12
src/main/scala/rocketchip/Periphery.scala
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@ -165,7 +165,7 @@ trait PeripheryMasterAXI4MMIOModule {
/////
// PeripherySlaveAXI4 is an example, make your own cake pattern like this one.
trait PeripherySlaveAXI4 extends L2Crossbar {
trait PeripherySlaveAXI4 extends TopNetwork {
private val config = p(ExtIn)
val l2_axi4 = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
masters = Seq(AXI4MasterParameters(
@ -179,12 +179,12 @@ trait PeripherySlaveAXI4 extends L2Crossbar {
l2_axi4))))
}
trait PeripherySlaveAXI4Bundle extends L2CrossbarBundle {
trait PeripherySlaveAXI4Bundle extends TopNetworkBundle {
val outer: PeripherySlaveAXI4
val l2_axi4 = outer.l2_axi4.bundleIn
}
trait PeripherySlaveAXI4Module extends L2CrossbarModule {
trait PeripherySlaveAXI4Module extends TopNetworkModule {
val outer: PeripherySlaveAXI4
val io: PeripherySlaveAXI4Bundle
// nothing to do
@ -231,7 +231,7 @@ trait PeripheryMasterTLMMIOModule {
/////
// NOTE: this port is NOT allowed to issue Acquires
trait PeripherySlaveTL extends L2Crossbar {
trait PeripherySlaveTL extends TopNetwork {
private val config = p(ExtIn)
val l2_tl = TLBlindInputNode(Seq(TLClientPortParameters(
clients = Seq(TLClientParameters(
@ -243,12 +243,12 @@ trait PeripherySlaveTL extends L2Crossbar {
l2_tl))
}
trait PeripherySlaveTLBundle extends L2CrossbarBundle {
trait PeripherySlaveTLBundle extends TopNetworkBundle {
val outer: PeripherySlaveTL
val l2_tl = outer.l2_tl.bundleIn
}
trait PeripherySlaveTLModule extends L2CrossbarModule {
trait PeripherySlaveTLModule extends TopNetworkModule {
val outer: PeripherySlaveTL
val io: PeripherySlaveTLBundle
// nothing to do