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rocketchip: pass variable l1tol2 connections into coreplex

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This commit is contained in:
Wesley W. Terpstra
2017-01-29 11:16:00 -08:00
parent d5fa159063
commit 24ee7f45f5
5 changed files with 16 additions and 41 deletions
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3
src/main/scala/coreplex/Coreplex.scala
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@ -11,17 +11,14 @@ import util._
class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex
with CoreplexRISCVPlatform
with HasL2MasterPort
with HasRocketTiles {
override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this))
}
class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
with CoreplexRISCVPlatformBundle
with HasL2MasterPortBundle
with HasRocketTilesBundle
class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
with CoreplexRISCVPlatformModule
with HasL2MasterPortModule
with HasRocketTilesModule