rocketchip: pass variable l1tol2 connections into coreplex

src/main/scala/coreplex/Coreplex.scala

@@ -11,17 +11,14 @@ import util._
 
 class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex
     with CoreplexRISCVPlatform
-    with HasL2MasterPort
     with HasRocketTiles {
   override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this))
 }
 
 class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
     with CoreplexRISCVPlatformBundle
-    with HasL2MasterPortBundle
     with HasRocketTilesBundle
 
 class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
     with CoreplexRISCVPlatformModule
-    with HasL2MasterPortModule
     with HasRocketTilesModule

src/main/scala/coreplex/CoreplexNetwork.scala

@@ -24,9 +24,13 @@ trait CoreplexNetwork extends HasCoreplexParameters {
 
   val mmio = TLOutputNode()
   val mmioInt = IntInputNode()
+  val l2in = TLInputNode()
 
   intBar.intnode := mmioInt
 
+  // Allows a variable number of inputs from outside to the Xbar
+  l1tol2.node :=* l2in
+
   cbus.node :=
     TLBuffer()(
     TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
@@ -43,6 +47,7 @@ trait CoreplexNetworkBundle extends HasCoreplexParameters {
 
   val mmio = outer.mmio.bundleOut
   val interrupts = outer.mmioInt.bundleIn
+  val l2in = outer.l2in.bundleIn
 }
 
 trait CoreplexNetworkModule extends HasCoreplexParameters {
@@ -93,21 +98,3 @@ trait BankedL2CoherenceManagersModule extends CoreplexNetworkModule {
   val outer: BankedL2CoherenceManagers
   val io: BankedL2CoherenceManagersBundle
 }
-
-/////
-
-trait HasL2MasterPort extends CoreplexNetwork {
-  val module: HasL2MasterPortModule
-  val l2in = TLInputNode()
-  l1tol2.node := TLBuffer()(l2in)
-}
-
-trait HasL2MasterPortBundle extends CoreplexNetworkBundle {
-  val outer: HasL2MasterPort
-  val l2in = outer.l2in.bundleIn
-}
-
-trait HasL2MasterPortModule extends CoreplexNetworkModule {
-  val outer: HasL2MasterPort
-  val io: HasL2MasterPortBundle
-}