From 11dbd4221a0dd2af5bbf401069ef7254f773455c Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Fri, 10 Apr 2015 17:53:47 -0700 Subject: [PATCH 1/6] Fixed front-end to support four-wide fetch. --- rocket/src/main/scala/icache.scala | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index d7a820db..b992dd5f 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -114,8 +114,13 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid) io.cpu.resp.bits.pc := s2_pc - - val fetch_data = icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits)) + var fetch_data:Bits = null + require (coreFetchWidth <= 4) + if (coreFetchWidth == 4) { + fetch_data = icache.io.resp.bits.datablock + } else { + fetch_data = icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits)) + } for (i <- 0 until coreFetchWidth) { io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits) } From 2f88c5ca9dcde6dd1dc9647c8dde22c2d70891da Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Sat, 11 Apr 2015 02:16:44 -0700 Subject: [PATCH 2/6] Renamed PCR to CSR --- rocket/src/main/scala/consts.scala | 2 +- rocket/src/main/scala/ctrl.scala | 6 +++--- rocket/src/main/scala/dpath.scala | 32 +++++++++++++++--------------- 3 files changed, 20 insertions(+), 20 deletions(-) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 030753d0..4d7cb68d 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -21,7 +21,7 @@ trait ScalarOpConstants { val PC_EX = UInt(0, 2) val PC_MEM = UInt(1, 2) val PC_WB = UInt(2, 2) - val PC_PCR = UInt(3, 2) + val PC_CSR = UInt(3, 2) val A1_X = Bits("b??", 2) val A1_ZERO = UInt(0, 2) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index b083371c..182d326c 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -553,7 +553,7 @@ class Control extends CoreModule take_pc_wb := replay_wb || wb_xcpt || io.dpath.eret io.dpath.sel_pc := - Mux(wb_xcpt || io.dpath.eret, PC_PCR, // exception or [m|s]ret + Mux(wb_xcpt || io.dpath.eret, PC_CSR, // exception or [m|s]ret Mux(replay_wb, PC_WB, // replay PC_MEM)) @@ -589,7 +589,7 @@ class Control extends CoreModule io.dpath.bypass_src(i) := PriorityEncoder(doBypass(i)) } - // stall for RAW/WAW hazards on PCRs, loads, AMOs, and mul/div in execute stage. + // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage. val id_renx1_not0 = id_ctrl.rxs1 && id_raddr1 != UInt(0) val id_renx2_not0 = id_ctrl.rxs2 && id_raddr2 != UInt(0) val id_wen_not0 = id_ctrl.wxd && id_waddr != UInt(0) @@ -605,7 +605,7 @@ class Control extends CoreModule io.fpu.dec.wen && id_waddr === io.dpath.ex_waddr) val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex) - // stall for RAW/WAW hazards on PCRs, LB/LH, and mul/div in memory stage. + // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage. val mem_mem_cmd_bh = if (params(FastLoadWord)) Bool(!params(FastLoadByte)) && mem_reg_slow_bypass else Bool(true) diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index bc25a1bd..a60ff72f 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -166,17 +166,17 @@ class Datapath extends CoreModule require(params(CoreDCacheReqTagBits) >= 6) // processor control regfile read - val pcr = Module(new CSRFile) - pcr.io.host <> io.host - pcr.io <> io.ctrl - pcr.io <> io.fpu - pcr.io.rocc <> io.rocc - pcr.io.pc := wb_reg_pc - pcr.io.uarch_counters.foreach(_ := Bool(false)) + val csr = Module(new CSRFile) + csr.io.host <> io.host + csr.io <> io.ctrl + csr.io <> io.fpu + csr.io.rocc <> io.rocc + csr.io.pc := wb_reg_pc + csr.io.uarch_counters.foreach(_ := Bool(false)) - io.ptw.ptbr := pcr.io.ptbr - io.ptw.invalidate := pcr.io.fatc - io.ptw.status := pcr.io.status + io.ptw.ptbr := csr.io.ptbr + io.ptw.invalidate := csr.io.fatc + io.ptw.status := csr.io.status // memory stage mem_reg_kill := ex_reg_kill @@ -246,7 +246,7 @@ class Datapath extends CoreModule } wb_wdata := Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data_subword, Mux(io.ctrl.ll_wen, ll_wdata, - Mux(io.ctrl.csr_cmd != CSR.N, pcr.io.rw.rdata, + Mux(io.ctrl.csr_cmd != CSR.N, csr.io.rw.rdata, wb_reg_wdata))) val wb_wen = io.ctrl.ll_wen || io.ctrl.wb_wen @@ -258,9 +258,9 @@ class Datapath extends CoreModule io.ctrl.fp_sboard_clra := dmem_resp_waddr // processor control regfile write - pcr.io.rw.addr := wb_reg_inst(31,20) - pcr.io.rw.cmd := io.ctrl.csr_cmd - pcr.io.rw.wdata := wb_reg_wdata + csr.io.rw.addr := wb_reg_inst(31,20) + csr.io.rw.cmd := io.ctrl.csr_cmd + csr.io.rw.wdata := wb_reg_wdata io.rocc.cmd.bits.inst := new RoCCInstruction().fromBits(wb_reg_inst) io.rocc.cmd.bits.rs1 := wb_reg_wdata @@ -269,7 +269,7 @@ class Datapath extends CoreModule // hook up I$ io.imem.req.bits.pc := Mux(io.ctrl.sel_pc === PC_MEM, mem_npc, - Mux(io.ctrl.sel_pc === PC_PCR, pcr.io.evec, + Mux(io.ctrl.sel_pc === PC_CSR, csr.io.evec, wb_reg_pc)).toUInt // PC_WB io.imem.btb_update.bits.pc := mem_reg_pc io.imem.btb_update.bits.target := io.imem.req.bits.pc @@ -283,7 +283,7 @@ class Datapath extends CoreModule io.ctrl.wb_waddr := wb_reg_inst(11,7) printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", - io.host.id, pcr.io.time(32,0), io.ctrl.retire, wb_reg_pc, + io.host.id, csr.io.time(32,0), io.ctrl.retire, wb_reg_pc, Mux(wb_wen, wb_waddr, UInt(0)), wb_wdata, wb_wen, wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))), wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))), From 8fc2d38ca90093f11192ba8bd54f093b97ac242a Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Sat, 11 Apr 2015 02:20:34 -0700 Subject: [PATCH 3/6] Removed unnecessary signal in CSRIO --- rocket/src/main/scala/csr.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala index 8e0c875a..fa263d19 100644 --- a/rocket/src/main/scala/csr.scala +++ b/rocket/src/main/scala/csr.scala @@ -93,7 +93,6 @@ class CSRFileIO extends CoreBundle { val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+retireWidth))) val custom_mrw_csrs = Vec.fill(params(NCustomMRWCSRs))(UInt(INPUT, xLen)) val cause = UInt(INPUT, xLen) - val mbadaddr_wen = Bool(INPUT) val pc = SInt(INPUT, vaddrBits+1) val fatc = Bool(OUTPUT) val time = UInt(OUTPUT, xLen) From a564f08702593b59b17f3cac5636e9924ed7dcc4 Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Sat, 11 Apr 2015 02:26:33 -0700 Subject: [PATCH 4/6] Rename dmem.sret signal to more accurate invalidate_lr --- rocket/src/main/scala/ctrl.scala | 2 +- rocket/src/main/scala/nbdcache.scala | 4 ++-- rocket/src/main/scala/rocc.scala | 2 +- rocket/src/main/scala/tile.scala | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 182d326c..3e0e3a8c 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -674,7 +674,7 @@ class Control extends CoreModule io.dmem.req.bits.cmd := ex_ctrl.mem_cmd io.dmem.req.bits.typ := ex_ctrl.mem_type io.dmem.req.bits.phys := Bool(false) - io.dmem.sret := wb_xcpt // obviously not an sret, but sufficient + io.dmem.invalidate_lr := wb_xcpt io.rocc.cmd.valid := wb_rocc_val io.rocc.exception := wb_xcpt && io.dpath.status.xs.orR diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 3f24ba4c..fa82b485 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -83,7 +83,7 @@ class HellaCacheIO extends CoreBundle { val resp = Valid(new HellaCacheResp).flip val replay_next = Valid(Bits(width = coreDCacheReqTagBits)).flip val xcpt = (new HellaCacheExceptions).asInput - val sret = Bool(OUTPUT) + val invalidate_lr = Bool(OUTPUT) val ordered = Bool(INPUT) } @@ -752,7 +752,7 @@ class HellaCache extends L1HellaCacheModule { lrsc_count := 0 } } - when (io.cpu.sret) { lrsc_count := 0 } + when (io.cpu.invalidate_lr) { lrsc_count := 0 } val s2_data = Vec.fill(nWays){Bits(width = encRowBits)} for (w <- 0 until nWays) { diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala index 0f044dae..79332c32 100644 --- a/rocket/src/main/scala/rocc.scala +++ b/rocket/src/main/scala/rocc.scala @@ -123,7 +123,7 @@ class AccumulatorExample extends RoCC io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores) io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1 io.mem.req.bits.data := Bits(0) // we're not performing any stores... - io.mem.sret := false + io.mem.invalidate_lr := false io.imem.acquire.valid := false io.imem.grant.ready := false diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index def17452..edb5566c 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -25,7 +25,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) { val ptw = Module(new PTW(params(NPTWPorts))) val core = Module(new Core, { case CoreName => "Rocket" }) - dcache.io.cpu.sret := core.io.dmem.sret // Bypass sret to dcache + dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr // Bypass signal to dcache val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts))) dcArb.io.requestor(0) <> ptw.io.mem dcArb.io.requestor(1) <> core.io.dmem From 4d6ebded02f182e31912f7b696a3cdece1e198a4 Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Sat, 11 Apr 2015 02:58:34 -0700 Subject: [PATCH 5/6] Added assert to nbdcache --- rocket/src/main/scala/nbdcache.scala | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index fa82b485..3b55ec8c 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -686,6 +686,10 @@ class HellaCache extends L1HellaCacheModule { io.cpu.xcpt.pf.ld := s1_read && dtlb.io.resp.xcpt_ld io.cpu.xcpt.pf.st := s1_write && dtlb.io.resp.xcpt_st + assert (!(Reg(next= + (io.cpu.xcpt.ma.ld || io.cpu.xcpt.ma.st || io.cpu.xcpt.pf.ld || io.cpu.xcpt.pf.st)) && + io.cpu.resp.valid), "DCache exception occurred - cache response not killed.") + // tags def onReset = L1Metadata(UInt(0), ClientMetadata.onReset) val meta = Module(new MetadataArray(onReset _)) From 517d0d4b897c7d5da8dbdc6ef14435696dc5a8f9 Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Sun, 12 Apr 2015 18:44:03 -0700 Subject: [PATCH 6/6] feedback on PR --- rocket/src/main/scala/icache.scala | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index b992dd5f..1103f22d 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -114,13 +114,11 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid) io.cpu.resp.bits.pc := s2_pc - var fetch_data:Bits = null - require (coreFetchWidth <= 4) - if (coreFetchWidth == 4) { - fetch_data = icache.io.resp.bits.datablock - } else { - fetch_data = icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits)) - } + require(coreFetchWidth * coreInstBytes <= rowBytes) + val fetch_data = + if (coreFetchWidth * coreInstBytes == rowBytes) icache.io.resp.bits.datablock + else icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits)) + for (i <- 0 until coreFetchWidth) { io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits) }