riscv/rocket-chip
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Chisel3 compatibility fixes

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This commit is contained in:
Andrew Waterman 2015-09-11 15:41:39 -07:00
parent 350d530766
commit 24389a5257
1 changed files with 14 additions and 13 deletions
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27
uncore/src/main/scala/cache.scala
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@ -145,22 +145,22 @@ class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
val io = new Bundle {
val read = Decoupled(new MetaReadReq).flip
val write = Decoupled(new MetaWriteReq(rstVal)).flip
val resp = Vec(rstVal.cloneType.asOutput, nWays)
val resp = Vec(rstVal.cloneType, nWays).asOutput
}
val rst_cnt = Reg(init=UInt(0, log2Up(nSets+1)))
val rst = rst_cnt < UInt(nSets)
val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
val wdata = Mux(rst, rstVal, io.write.bits.data).toBits
val wmask = Mux(rst, SInt(-1), io.write.bits.way_en.toSInt).toUInt
val wmask = Mux(rst, SInt(-1), io.write.bits.way_en.toSInt).toBools
when (rst) { rst_cnt := rst_cnt+UInt(1) }
val metabits = rstVal.getWidth
val tag_arr = SeqMem(UInt(width = metabits*nWays), nSets)
val tag_arr = SeqMem(Vec(UInt(width = metabits), nWays), nSets)
when (rst || io.write.valid) {
tag_arr.write(waddr, Fill(nWays, wdata), FillInterleaved(metabits, wmask))
tag_arr.write(waddr, Vec.fill(nWays)(wdata), wmask)
}
val tags = tag_arr.read(io.read.bits.idx, io.read.valid)
val tags = tag_arr.read(io.read.bits.idx, io.read.valid).toBits
io.resp := io.resp.fromBits(tags)
io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
io.write.ready := !rst
@ -318,16 +318,17 @@ class L2DataRWIO extends L2HellaCacheBundle with HasL2DataReadIO with HasL2DataW
class L2DataArray(delay: Int) extends L2HellaCacheModule {
val io = new L2DataRWIO().flip
val array = SeqMem(Bits(width=rowBits), nWays*nSets*refillCycles)
val array = SeqMem(Vec(Bits(width=8), rowBits/8), nWays*nSets*refillCycles)
val ren = !io.write.valid && io.read.valid
val raddr = Cat(OHToUInt(io.read.bits.way_en), io.read.bits.addr_idx, io.read.bits.addr_beat)
val waddr = Cat(OHToUInt(io.write.bits.way_en), io.write.bits.addr_idx, io.write.bits.addr_beat)
val wmask = FillInterleaved(8, io.write.bits.wmask)
when (io.write.valid) { array.write(waddr, io.write.bits.data, wmask) }
val wdata = Vec.tabulate(rowBits/8)(i => io.write.bits.data(8*(i+1)-1,8*i))
val wmask = io.write.bits.wmask.toBools
when (io.write.valid) { array.write(waddr, wdata, wmask) }
val r_req = Pipe(io.read.fire(), io.read.bits)
io.resp := Pipe(r_req.valid, r_req.bits, delay)
io.resp.bits.data := Pipe(r_req.valid, array.read(raddr, ren), delay).bits
io.resp.bits.data := Pipe(r_req.valid, array.read(raddr, ren).toBits, delay).bits
io.read.ready := !io.write.valid
io.write.ready := Bool(true)
}
@ -339,11 +340,11 @@ class L2HellaCacheBank extends HierarchicalCoherenceAgent with L2HellaCacheParam
val meta = Module(new L2MetadataArray) // TODO: add delay knob
val data = Module(new L2DataArray(1))
val tshrfile = Module(new TSHRFile)
tshrfile.io.inner <> io.inner
io.inner <> tshrfile.io.inner
io.outer <> tshrfile.io.outer
io.incoherent <> tshrfile.io.incoherent
tshrfile.io.meta <> meta.io
tshrfile.io.data <> data.io
tshrfile.io.incoherent <> io.incoherent
meta.io <> tshrfile.io.meta
data.io <> tshrfile.io.data
}
class TSHRFileIO extends HierarchicalTLIO {