Merge branch 'master' into tilelink2.2
This commit is contained in:
Andrew Waterman
GitHub
commit
23d0b31615
2
firrtl
2
firrtl
@ -1 +1 @@
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Subproject commit a2af16c1fb1f5166eab34188df9944012da3cbc3
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Subproject commit 6a05468ed0ece1ace3019666b16f2ae83ef76ef9
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@ -1 +1 @@
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Subproject commit 61d74b5837d270f116fc21e907ed78f582361688
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Subproject commit 4d7e0824dbc1d57d0ff987a4499bd118b3dbe563
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@ -79,12 +79,16 @@ class BaseCoreplexConfig extends Config (
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case BuildTiles => {
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val env = if(site(UseVM)) List("p","v") else List("p")
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site(FPUKey) foreach { case cfg =>
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TestGeneration.addSuite(rv32udBenchmarks)
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TestGeneration.addSuites(env.map(rv64ufNoDiv))
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TestGeneration.addSuites(env.map(rv64udNoDiv))
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if (cfg.divSqrt) {
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TestGeneration.addSuites(env.map(rv64uf))
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TestGeneration.addSuites(env.map(rv64ud))
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if (site(XLen) == 32) {
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TestGeneration.addSuites(env.map(rv32ufNoDiv))
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} else {
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TestGeneration.addSuite(rv32udBenchmarks)
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TestGeneration.addSuites(env.map(rv64ufNoDiv))
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TestGeneration.addSuites(env.map(rv64udNoDiv))
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if (cfg.divSqrt) {
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TestGeneration.addSuites(env.map(rv64uf))
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TestGeneration.addSuites(env.map(rv64ud))
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}
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}
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}
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if (site(UseAtomics)) TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64ua else rv32ua))
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@ -329,10 +333,7 @@ class WithNL2Ways(n: Int) extends Config(
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class WithRV32 extends Config(
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(pname,site,here) => pname match {
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case XLen => 32
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case UseVM => false
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case UseUser => false
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case UseAtomics => false
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case FPUKey => None
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case FPUKey => Some(FPUConfig(divSqrt = false))
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case RegressionTestNames => LinkedHashSet(
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"rv32mi-p-ma_addr",
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"rv32mi-p-csr",
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@ -353,14 +354,16 @@ class WithBlockingL1 extends Config (
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)
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class WithSmallCores extends Config (
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topDefinitions = { (pname,site,here) => pname match {
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case MulDivKey => Some(MulDivConfig())
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case FPUKey => None
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case NTLBEntries => 4
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case BtbKey => BtbParameters(nEntries = 0)
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case NAcquireTransactors => 2
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case _ => throw new CDEMatchError
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}},
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topDefinitions = { (pname,site,here) => pname match {
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case MulDivKey => Some(MulDivConfig())
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case FPUKey => None
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case UseVM => false
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case UseUser => false
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case NTLBEntries => 4
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case BtbKey => BtbParameters(nEntries = 0)
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case NAcquireTransactors => 2
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case _ => throw new CDEMatchError
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}},
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knobValues = {
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case "L1D_SETS" => 64
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case "L1D_WAYS" => 1
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@ -144,6 +144,8 @@ object DefaultTestSuites {
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val rv64uf = new AssemblyTestSuite("rv64uf", rv64ufNames)(_)
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val rv64ufNoDiv = new AssemblyTestSuite("rv64uf", rv64ufNames - "fdiv")(_)
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val rv32ufNoDiv = new AssemblyTestSuite("rv32uf", rv64ufNames - "fdiv")(_)
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val rv64udNames = rv64ufNames + "structural"
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val rv64ud = new AssemblyTestSuite("rv64ud", rv64udNames)(_)
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val rv64udNoDiv = new AssemblyTestSuite("rv64ud", rv64udNames - "fdiv")(_)
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@ -77,8 +77,6 @@ class AddrMap(
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var cacheable = true
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for (AddrMapEntry(name, r) <- entriesIn) {
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if (r.start != 0) {
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val align = BigInt(1) << log2Ceil(r.size)
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require(r.start >= base, s"region $name base address 0x${r.start.toString(16)} overlaps previous base 0x${base.toString(16)}")
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base = r.start
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} else {
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base = (base + r.size - 1) / r.size * r.size
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@ -121,6 +119,16 @@ class AddrMap(
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}.flatten.sortBy(_.region.start)
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}
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// checks to see whether any MemRange overlaps within this AddrMap
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flatten.combinations(2) foreach {
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case (Seq(AddrMapEntry(an, ar), AddrMapEntry(bn, br))) =>
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val arEnd = ar.start + ar.size
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val brEnd = br.start + br.size
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val abOverlaps = ar.start < brEnd && br.start < arEnd
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require(!abOverlaps,
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"region $an@0x${ar.start.toString(16)} overlaps region $bn@0x${br.start.toString(16)}")
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}
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def toRange: MemRange = MemRange(start, size, attr)
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def apply(name: String): MemRegion = mapping(name)
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def contains(name: String): Boolean = mapping.contains(name)
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@ -11,7 +11,7 @@ import uncore.util._
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case object BtbKey extends Field[BtbParameters]
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case class BtbParameters(
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nEntries: Int = 62,
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nEntries: Int = 40,
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nRAS: Int = 2,
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updatesOutOfOrder: Boolean = false)
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@ -260,11 +260,13 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val cpu_ren = io.rw.cmd =/= CSR.N && !system_insn
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val cpu_wen = cpu_ren && io.rw.cmd =/= CSR.R
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val isa_string = "IM" +
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val isa_string = "I" +
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(if (usingMulDiv) "M" else "") +
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(if (usingAtomics) "A" else "") +
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(if (usingFPU) "F" else "") +
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(if (usingFPU && xLen > 32) "D" else "") +
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(if (usingVM) "S" else "") +
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(if (usingUser) "U" else "") +
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(if (usingAtomics) "A" else "") +
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(if (usingFPU) "FD" else "") +
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(if (usingRoCC) "X" else "")
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val isa = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) |
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isa_string.map(x => 1 << (x - 'A')).reduce(_|_)
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@ -239,7 +239,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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metaWriteArb.io.in(0).valid := (s2_valid_hit && s2_update_meta) || (s2_victimize && !s2_victim_dirty)
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metaWriteArb.io.in(0).bits.way_en := s2_victim_way
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metaWriteArb.io.in(0).bits.idx := s2_req.addr(idxMSB, idxLSB)
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metaWriteArb.io.in(0).bits.data.coh := Mux(s2_hit, s2_new_hit_state, ClientMetadata.onReset)
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metaWriteArb.io.in(0).bits.data.coh := Mux(s2_valid_hit, s2_new_hit_state, ClientMetadata.onReset)
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metaWriteArb.io.in(0).bits.data.tag := s2_req.addr(paddrBits-1, untagBits)
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// acquire
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@ -345,7 +345,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val newCoh = Wire(init = probeNewCoh)
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releaseWay := s2_probe_way
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when (s2_victimize && s2_victim_dirty) {
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assert(!s2_hit_state.isValid())
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assert(!(s2_valid && s2_hit_state.isValid()))
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release_state := s_voluntary_writeback
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probe_bits.addr_block := Cat(s2_victim_tag, s2_req.addr(idxMSB, idxLSB))
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}
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@ -42,8 +42,7 @@ object FPConstants
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val FLAGS_SZ = 5
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}
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class FPUCtrlSigs extends Bundle
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{
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trait HasFPUCtrlSigs {
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val cmd = Bits(width = FCMD_WIDTH)
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val ldst = Bool()
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val wen = Bool()
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@ -63,78 +62,85 @@ class FPUCtrlSigs extends Bundle
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val wflags = Bool()
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}
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class FPUDecoder extends Module
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{
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class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
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class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
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val io = new Bundle {
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val inst = Bits(INPUT, 32)
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val sigs = new FPUCtrlSigs().asOutput
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}
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val decoder = DecodeLogic(io.inst,
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List (FCMD_X, X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X),
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val default = List(FCMD_X, X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X)
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val f =
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Array(FLW -> List(FCMD_X, Y,Y,N,N,N,X,X,Y,N,N,N,N,N,N,N,N),
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FLD -> List(FCMD_X, Y,Y,N,N,N,X,X,N,N,N,N,N,N,N,N,N),
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FSW -> List(FCMD_MV_XF, Y,N,N,Y,N,Y,X,Y,N,Y,N,N,N,N,N,N),
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FSD -> List(FCMD_MV_XF, Y,N,N,Y,N,Y,X,N,N,Y,N,N,N,N,N,N),
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FMV_S_X -> List(FCMD_MV_FX, N,Y,N,N,N,X,X,Y,Y,N,N,N,N,N,Y,N),
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FMV_D_X -> List(FCMD_MV_FX, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,Y,N),
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FCVT_S_W -> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,Y,Y,N,N,N,N,N,Y,Y),
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FCVT_S_WU-> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,Y,Y,N,N,N,N,N,Y,Y),
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FCVT_S_L -> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,Y,Y,N,N,N,N,N,Y,Y),
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FCVT_S_LU-> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,Y,Y,N,N,N,N,N,Y,Y),
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FCVT_D_W -> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,Y,Y),
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FCVT_D_WU-> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,Y,Y),
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FCVT_D_L -> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,Y,Y),
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FCVT_D_LU-> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,Y,Y),
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FMV_X_S -> List(FCMD_MV_XF, N,N,Y,N,N,N,X,Y,N,Y,N,N,N,N,Y,N),
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FMV_X_D -> List(FCMD_MV_XF, N,N,Y,N,N,N,X,N,N,Y,N,N,N,N,Y,N),
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FCLASS_S -> List(FCMD_MV_XF, N,N,Y,N,N,N,X,Y,N,Y,N,N,N,N,Y,N),
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FCLASS_D -> List(FCMD_MV_XF, N,N,Y,N,N,N,X,N,N,Y,N,N,N,N,Y,N),
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FCVT_W_S -> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,Y,N,Y,N,N,N,N,Y,Y),
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FCVT_WU_S-> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,Y,N,Y,N,N,N,N,Y,Y),
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FCVT_L_S -> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,Y,N,Y,N,N,N,N,Y,Y),
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FCVT_LU_S-> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,Y,N,Y,N,N,N,N,Y,Y),
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FEQ_S -> List(FCMD_CMP, N,N,Y,Y,N,N,N,Y,N,Y,N,N,N,N,N,Y),
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FLT_S -> List(FCMD_CMP, N,N,Y,Y,N,N,N,Y,N,Y,N,N,N,N,N,Y),
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FLE_S -> List(FCMD_CMP, N,N,Y,Y,N,N,N,Y,N,Y,N,N,N,N,N,Y),
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FSGNJ_S -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,N,N),
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FSGNJN_S -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,N,N),
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FSGNJX_S -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,N,N),
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FMIN_S -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,N,Y),
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FMAX_S -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,N,Y),
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FADD_S -> List(FCMD_ADD, N,Y,Y,Y,N,N,Y,Y,N,N,N,Y,N,N,Y,Y),
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FSUB_S -> List(FCMD_SUB, N,Y,Y,Y,N,N,Y,Y,N,N,N,Y,N,N,Y,Y),
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FMUL_S -> List(FCMD_MUL, N,Y,Y,Y,N,N,N,Y,N,N,N,Y,N,N,Y,Y),
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FMADD_S -> List(FCMD_MADD, N,Y,Y,Y,Y,N,N,Y,N,N,N,Y,N,N,Y,Y),
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FMSUB_S -> List(FCMD_MSUB, N,Y,Y,Y,Y,N,N,Y,N,N,N,Y,N,N,Y,Y),
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FNMADD_S -> List(FCMD_NMADD, N,Y,Y,Y,Y,N,N,Y,N,N,N,Y,N,N,Y,Y),
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FNMSUB_S -> List(FCMD_NMSUB, N,Y,Y,Y,Y,N,N,Y,N,N,N,Y,N,N,Y,Y),
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FDIV_S -> List(FCMD_DIV, N,Y,Y,Y,N,N,N,Y,N,N,N,N,Y,N,Y,Y),
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||||
FSQRT_S -> List(FCMD_SQRT, N,Y,Y,N,N,Y,X,Y,N,N,N,N,N,Y,Y,Y))
|
||||
val d =
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||||
Array(FLD -> List(FCMD_X, Y,Y,N,N,N,X,X,N,N,N,N,N,N,N,N,N),
|
||||
FSD -> List(FCMD_MV_XF, Y,N,N,Y,N,Y,X,N,N,Y,N,N,N,N,N,N),
|
||||
FMV_D_X -> List(FCMD_MV_FX, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,Y,N),
|
||||
FCVT_D_W -> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,Y,Y),
|
||||
FCVT_D_WU-> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,Y,Y),
|
||||
FCVT_D_L -> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,Y,Y),
|
||||
FCVT_D_LU-> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,Y,Y),
|
||||
FMV_X_D -> List(FCMD_MV_XF, N,N,Y,N,N,N,X,N,N,Y,N,N,N,N,Y,N),
|
||||
FCLASS_D -> List(FCMD_MV_XF, N,N,Y,N,N,N,X,N,N,Y,N,N,N,N,Y,N),
|
||||
FCVT_W_D -> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,N,N,Y,N,N,N,N,Y,Y),
|
||||
FCVT_WU_D-> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,N,N,Y,N,N,N,N,Y,Y),
|
||||
FCVT_L_D -> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,N,N,Y,N,N,N,N,Y,Y),
|
||||
FCVT_LU_D-> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,N,N,Y,N,N,N,N,Y,Y),
|
||||
FCVT_S_D -> List(FCMD_CVT_FF, N,Y,Y,N,N,N,X,Y,N,N,Y,N,N,N,Y,Y),
|
||||
FCVT_D_S -> List(FCMD_CVT_FF, N,Y,Y,N,N,N,X,N,N,N,Y,N,N,N,Y,Y),
|
||||
FEQ_S -> List(FCMD_CMP, N,N,Y,Y,N,N,N,Y,N,Y,N,N,N,N,N,Y),
|
||||
FLT_S -> List(FCMD_CMP, N,N,Y,Y,N,N,N,Y,N,Y,N,N,N,N,N,Y),
|
||||
FLE_S -> List(FCMD_CMP, N,N,Y,Y,N,N,N,Y,N,Y,N,N,N,N,N,Y),
|
||||
FEQ_D -> List(FCMD_CMP, N,N,Y,Y,N,N,N,N,N,Y,N,N,N,N,N,Y),
|
||||
FLT_D -> List(FCMD_CMP, N,N,Y,Y,N,N,N,N,N,Y,N,N,N,N,N,Y),
|
||||
FLE_D -> List(FCMD_CMP, N,N,Y,Y,N,N,N,N,N,Y,N,N,N,N,N,Y),
|
||||
FSGNJ_S -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,N,N),
|
||||
FSGNJN_S -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,N,N),
|
||||
FSGNJX_S -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,N,N),
|
||||
FSGNJ_D -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,N,N,N,Y,N,N,N,N,N),
|
||||
FSGNJN_D -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,N,N,N,Y,N,N,N,N,N),
|
||||
FSGNJX_D -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,N,N,N,Y,N,N,N,N,N),
|
||||
FMIN_S -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,N,Y),
|
||||
FMAX_S -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,N,Y),
|
||||
FMIN_D -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,N,N,N,N,Y,N,N,N,N,Y),
|
||||
FMAX_D -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,N,N,N,N,Y,N,N,N,N,Y),
|
||||
FADD_S -> List(FCMD_ADD, N,Y,Y,Y,N,N,Y,Y,N,N,N,Y,N,N,Y,Y),
|
||||
FSUB_S -> List(FCMD_SUB, N,Y,Y,Y,N,N,Y,Y,N,N,N,Y,N,N,Y,Y),
|
||||
FMUL_S -> List(FCMD_MUL, N,Y,Y,Y,N,N,N,Y,N,N,N,Y,N,N,Y,Y),
|
||||
FADD_D -> List(FCMD_ADD, N,Y,Y,Y,N,N,Y,N,N,N,N,Y,N,N,Y,Y),
|
||||
FSUB_D -> List(FCMD_SUB, N,Y,Y,Y,N,N,Y,N,N,N,N,Y,N,N,Y,Y),
|
||||
FMUL_D -> List(FCMD_MUL, N,Y,Y,Y,N,N,N,N,N,N,N,Y,N,N,Y,Y),
|
||||
FMADD_S -> List(FCMD_MADD, N,Y,Y,Y,Y,N,N,Y,N,N,N,Y,N,N,Y,Y),
|
||||
FMSUB_S -> List(FCMD_MSUB, N,Y,Y,Y,Y,N,N,Y,N,N,N,Y,N,N,Y,Y),
|
||||
FNMADD_S -> List(FCMD_NMADD, N,Y,Y,Y,Y,N,N,Y,N,N,N,Y,N,N,Y,Y),
|
||||
FNMSUB_S -> List(FCMD_NMSUB, N,Y,Y,Y,Y,N,N,Y,N,N,N,Y,N,N,Y,Y),
|
||||
FMADD_D -> List(FCMD_MADD, N,Y,Y,Y,Y,N,N,N,N,N,N,Y,N,N,Y,Y),
|
||||
FMSUB_D -> List(FCMD_MSUB, N,Y,Y,Y,Y,N,N,N,N,N,N,Y,N,N,Y,Y),
|
||||
FNMADD_D -> List(FCMD_NMADD, N,Y,Y,Y,Y,N,N,N,N,N,N,Y,N,N,Y,Y),
|
||||
FNMSUB_D -> List(FCMD_NMSUB, N,Y,Y,Y,Y,N,N,N,N,N,N,Y,N,N,Y,Y),
|
||||
FDIV_S -> List(FCMD_DIV, N,Y,Y,Y,N,N,N,Y,N,N,N,N,Y,N,Y,Y),
|
||||
FSQRT_S -> List(FCMD_SQRT, N,Y,Y,N,N,Y,X,Y,N,N,N,N,N,Y,Y,Y),
|
||||
FDIV_D -> List(FCMD_DIV, N,Y,Y,Y,N,N,N,N,N,N,N,N,Y,N,Y,Y),
|
||||
FSQRT_D -> List(FCMD_SQRT, N,Y,Y,N,N,Y,X,N,N,N,N,N,N,Y,Y,Y)
|
||||
))
|
||||
FSQRT_D -> List(FCMD_SQRT, N,Y,Y,N,N,Y,X,N,N,N,N,N,N,Y,Y,Y))
|
||||
|
||||
val insns = fLen match {
|
||||
case 32 => f
|
||||
case 64 => f ++ d
|
||||
}
|
||||
val decoder = DecodeLogic(io.inst, default, insns)
|
||||
val s = io.sigs
|
||||
val sigs = Seq(s.cmd, s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
|
||||
s.swap23, s.single, s.fromint, s.toint, s.fastpipe, s.fma,
|
||||
@ -149,13 +155,13 @@ class FPUIO(implicit p: Parameters) extends CoreBundle {
|
||||
val fcsr_rm = Bits(INPUT, FPConstants.RM_SZ)
|
||||
val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ))
|
||||
|
||||
val store_data = Bits(OUTPUT, 64)
|
||||
val store_data = Bits(OUTPUT, fLen)
|
||||
val toint_data = Bits(OUTPUT, xLen)
|
||||
|
||||
val dmem_resp_val = Bool(INPUT)
|
||||
val dmem_resp_type = Bits(INPUT, 3)
|
||||
val dmem_resp_tag = UInt(INPUT, 5)
|
||||
val dmem_resp_data = Bits(INPUT, 64)
|
||||
val dmem_resp_data = Bits(INPUT, fLen)
|
||||
|
||||
val valid = Bool(INPUT)
|
||||
val fcsr_rdy = Bool(OUTPUT)
|
||||
@ -172,18 +178,19 @@ class FPUIO(implicit p: Parameters) extends CoreBundle {
|
||||
val cp_resp = Decoupled(new FPResult())
|
||||
}
|
||||
|
||||
class FPResult extends Bundle
|
||||
{
|
||||
val data = Bits(width = 65)
|
||||
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
|
||||
val data = Bits(width = fLen+1)
|
||||
val exc = Bits(width = 5)
|
||||
}
|
||||
|
||||
class FPInput extends FPUCtrlSigs {
|
||||
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
|
||||
val rm = Bits(width = 3)
|
||||
val typ = Bits(width = 2)
|
||||
val in1 = Bits(width = 65)
|
||||
val in2 = Bits(width = 65)
|
||||
val in3 = Bits(width = 65)
|
||||
val in1 = Bits(width = fLen+1)
|
||||
val in2 = Bits(width = fLen+1)
|
||||
val in3 = Bits(width = fLen+1)
|
||||
|
||||
override def cloneType = new FPInput().asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
object ClassifyRecFN {
|
||||
@ -211,66 +218,101 @@ object ClassifyRecFN {
|
||||
}
|
||||
}
|
||||
|
||||
class FPToInt extends Module
|
||||
{
|
||||
object IsNaNRecFN {
|
||||
def apply(expWidth: Int, sigWidth: Int, in: UInt) =
|
||||
in(sigWidth + expWidth - 1, sigWidth + expWidth - 3).andR
|
||||
}
|
||||
|
||||
object IsSNaNRecFN {
|
||||
def apply(expWidth: Int, sigWidth: Int, in: UInt) =
|
||||
IsNaNRecFN(expWidth, sigWidth, in) && !in(sigWidth - 2)
|
||||
}
|
||||
|
||||
/** Format conversion without rounding or NaN handling */
|
||||
object RecFNToRecFN_noncompliant {
|
||||
def apply(in: UInt, inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) = {
|
||||
val sign = in(inSigWidth + inExpWidth)
|
||||
val fractIn = in(inSigWidth - 2, 0)
|
||||
val expIn = in(inSigWidth + inExpWidth - 1, inSigWidth - 1)
|
||||
val fractOut = fractIn << outSigWidth >> inSigWidth
|
||||
val expOut = {
|
||||
val expCode = expIn(inExpWidth, inExpWidth - 2)
|
||||
val commonCase = (expIn + (1 << outExpWidth)) - (1 << inExpWidth)
|
||||
Mux(expCode === 0 || expCode >= 6, Cat(expCode, commonCase(outExpWidth - 3, 0)),
|
||||
commonCase(outExpWidth, 0))
|
||||
}
|
||||
Cat(sign, expOut, fractOut)
|
||||
}
|
||||
}
|
||||
|
||||
trait HasFPUParameters {
|
||||
val fLen: Int
|
||||
val (sExpWidth, sSigWidth) = (8, 24)
|
||||
val (dExpWidth, dSigWidth) = (11, 53)
|
||||
val (maxExpWidth, maxSigWidth) = fLen match {
|
||||
case 32 => (sExpWidth, sSigWidth)
|
||||
case 64 => (dExpWidth, dSigWidth)
|
||||
}
|
||||
}
|
||||
|
||||
abstract class FPUModule(implicit p: Parameters) extends CoreModule()(p) with HasFPUParameters
|
||||
|
||||
class FPToInt(implicit p: Parameters) extends FPUModule()(p) {
|
||||
class Output extends Bundle {
|
||||
val lt = Bool()
|
||||
val store = Bits(width = fLen)
|
||||
val toint = Bits(width = xLen)
|
||||
val exc = Bits(width = 5)
|
||||
override def cloneType = new Output().asInstanceOf[this.type]
|
||||
}
|
||||
val io = new Bundle {
|
||||
val in = Valid(new FPInput).flip
|
||||
val as_double = new FPInput().asOutput
|
||||
val out = Valid(new Bundle {
|
||||
val lt = Bool()
|
||||
val store = Bits(width = 64)
|
||||
val toint = Bits(width = 64)
|
||||
val exc = Bits(width = 5)
|
||||
})
|
||||
val out = Valid(new Output)
|
||||
}
|
||||
|
||||
val in = Reg(new FPInput)
|
||||
val valid = Reg(next=io.in.valid)
|
||||
|
||||
def upconvert(x: UInt) = {
|
||||
val s2d = Module(new hardfloat.RecFNToRecFN(8, 24, 11, 53))
|
||||
s2d.io.in := x
|
||||
s2d.io.roundingMode := UInt(0)
|
||||
s2d.io.out
|
||||
}
|
||||
|
||||
val in1_upconvert = upconvert(io.in.bits.in1)
|
||||
val in2_upconvert = upconvert(io.in.bits.in2)
|
||||
def upconvert(x: UInt) = RecFNToRecFN_noncompliant(x, sExpWidth, sSigWidth, maxExpWidth, maxSigWidth)
|
||||
|
||||
when (io.in.valid) {
|
||||
in := io.in.bits
|
||||
when (io.in.bits.single && !io.in.bits.ldst && io.in.bits.cmd =/= FCMD_MV_XF) {
|
||||
in.in1 := in1_upconvert
|
||||
in.in2 := in2_upconvert
|
||||
if (fLen > 32) when (io.in.bits.single && !io.in.bits.ldst && io.in.bits.cmd =/= FCMD_MV_XF) {
|
||||
in.in1 := upconvert(io.in.bits.in1)
|
||||
in.in2 := upconvert(io.in.bits.in2)
|
||||
}
|
||||
}
|
||||
|
||||
val unrec_s = hardfloat.fNFromRecFN(8, 24, in.in1)
|
||||
val unrec_d = hardfloat.fNFromRecFN(11, 53, in.in1)
|
||||
val unrec_out = Mux(in.single, Cat(Fill(32, unrec_s(31)), unrec_s), unrec_d)
|
||||
val unrec_s = hardfloat.fNFromRecFN(sExpWidth, sSigWidth, in.in1).sextTo(xLen)
|
||||
val unrec_mem = fLen match {
|
||||
case 32 => unrec_s
|
||||
case 64 =>
|
||||
val unrec_d = hardfloat.fNFromRecFN(dExpWidth, dSigWidth, in.in1).sextTo(xLen)
|
||||
Mux(in.single, unrec_s, unrec_d)
|
||||
}
|
||||
val unrec_int = xLen match {
|
||||
case 32 => unrec_s
|
||||
case fLen => unrec_mem
|
||||
}
|
||||
|
||||
val classify_s = ClassifyRecFN(8, 24, in.in1)
|
||||
val classify_d = ClassifyRecFN(11, 53, in.in1)
|
||||
val classify_out = Mux(in.single, classify_s, classify_d)
|
||||
val classify_s = ClassifyRecFN(sExpWidth, sSigWidth, in.in1)
|
||||
val classify_out = fLen match {
|
||||
case 32 => classify_s
|
||||
case 64 =>
|
||||
val classify_d = ClassifyRecFN(dExpWidth, dSigWidth, in.in1)
|
||||
Mux(in.single, classify_s, classify_d)
|
||||
}
|
||||
|
||||
val dcmp = Module(new hardfloat.CompareRecFN(11, 53))
|
||||
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
|
||||
dcmp.io.a := in.in1
|
||||
dcmp.io.b := in.in2
|
||||
dcmp.io.signaling := Bool(true)
|
||||
val dcmp_out = (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR
|
||||
val dcmp_exc = dcmp.io.exceptionFlags
|
||||
|
||||
val d2l = Module(new hardfloat.RecFNToIN(11, 53, 64))
|
||||
val d2w = Module(new hardfloat.RecFNToIN(11, 53, 32))
|
||||
d2l.io.in := in.in1
|
||||
d2l.io.roundingMode := in.rm
|
||||
d2l.io.signedOut := ~in.typ(0)
|
||||
d2w.io.in := in.in1
|
||||
d2w.io.roundingMode := in.rm
|
||||
d2w.io.signedOut := ~in.typ(0)
|
||||
|
||||
io.out.bits.toint := Mux(in.rm(0), classify_out, unrec_out)
|
||||
io.out.bits.store := unrec_out
|
||||
io.out.bits.toint := Mux(in.rm(0), classify_out, unrec_int)
|
||||
io.out.bits.store := unrec_mem
|
||||
io.out.bits.exc := Bits(0)
|
||||
|
||||
when (in.cmd === FCMD_CMP) {
|
||||
@ -278,9 +320,18 @@ class FPToInt extends Module
|
||||
io.out.bits.exc := dcmp_exc
|
||||
}
|
||||
when (in.cmd === FCMD_CVT_IF) {
|
||||
io.out.bits.toint := Mux(in.typ(1), d2l.io.out.asSInt, d2w.io.out.asSInt).asUInt
|
||||
val dflags = Mux(in.typ(1), d2l.io.intExceptionFlags, d2w.io.intExceptionFlags)
|
||||
io.out.bits.exc := Cat(dflags(2, 1).orR, UInt(0, 3), dflags(0))
|
||||
val minXLen = 32
|
||||
val n = log2Ceil(xLen/minXLen) + 1
|
||||
for (i <- 0 until n) {
|
||||
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, minXLen << i))
|
||||
conv.io.in := in.in1
|
||||
conv.io.roundingMode := in.rm
|
||||
conv.io.signedOut := ~in.typ(0)
|
||||
when (in.typ.extract(log2Ceil(n), 1) === i) {
|
||||
io.out.bits.toint := conv.io.out.sextTo(xLen)
|
||||
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, UInt(0, 3), conv.io.intExceptionFlags(0))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
io.out.valid := valid
|
||||
@ -288,8 +339,7 @@ class FPToInt extends Module
|
||||
io.as_double := in
|
||||
}
|
||||
|
||||
class IntToFP(val latency: Int) extends Module
|
||||
{
|
||||
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
|
||||
val io = new Bundle {
|
||||
val in = Valid(new FPInput).flip
|
||||
val out = Valid(new FPResult)
|
||||
@ -299,91 +349,110 @@ class IntToFP(val latency: Int) extends Module
|
||||
|
||||
val mux = Wire(new FPResult)
|
||||
mux.exc := Bits(0)
|
||||
mux.data := hardfloat.recFNFromFN(11, 53, in.bits.in1)
|
||||
when (in.bits.single) {
|
||||
mux.data := Cat(SInt(-1, 32), hardfloat.recFNFromFN(8, 24, in.bits.in1))
|
||||
mux.data := hardfloat.recFNFromFN(sExpWidth, sSigWidth, in.bits.in1)
|
||||
if (fLen > 32) when (!in.bits.single) {
|
||||
mux.data := hardfloat.recFNFromFN(dExpWidth, dSigWidth, in.bits.in1)
|
||||
}
|
||||
|
||||
val longValue =
|
||||
Mux(in.bits.typ(1), in.bits.in1.asSInt,
|
||||
Mux(in.bits.typ(0), in.bits.in1(31,0).zext, in.bits.in1(31,0).asSInt))
|
||||
val l2s = Module(new hardfloat.INToRecFN(64, 8, 24))
|
||||
l2s.io.signedIn := ~in.bits.typ(0)
|
||||
l2s.io.in := longValue.asUInt
|
||||
l2s.io.roundingMode := in.bits.rm
|
||||
|
||||
val l2d = Module(new hardfloat.INToRecFN(64, 11, 53))
|
||||
l2d.io.signedIn := ~in.bits.typ(0)
|
||||
l2d.io.in := longValue.asUInt
|
||||
l2d.io.roundingMode := in.bits.rm
|
||||
val intValue = {
|
||||
val minXLen = 32
|
||||
val n = log2Ceil(xLen/minXLen) + 1
|
||||
val res = Wire(init = in.bits.in1.asSInt)
|
||||
for (i <- 0 until n-1) {
|
||||
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
|
||||
when (in.bits.typ.extract(log2Ceil(n), 1) === i) {
|
||||
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
|
||||
}
|
||||
}
|
||||
res.asUInt
|
||||
}
|
||||
|
||||
when (in.bits.cmd === FCMD_CVT_FI) {
|
||||
when (in.bits.single) {
|
||||
mux.data := Cat(SInt(-1, 32), l2s.io.out)
|
||||
mux.exc := l2s.io.exceptionFlags
|
||||
}.otherwise {
|
||||
mux.data := l2d.io.out
|
||||
mux.exc := l2d.io.exceptionFlags
|
||||
val l2s = Module(new hardfloat.INToRecFN(xLen, sExpWidth, sSigWidth))
|
||||
l2s.io.signedIn := ~in.bits.typ(0)
|
||||
l2s.io.in := intValue
|
||||
l2s.io.roundingMode := in.bits.rm
|
||||
mux.data := Cat(UInt((BigInt(1) << (fLen - 32)) - 1), l2s.io.out)
|
||||
mux.exc := l2s.io.exceptionFlags
|
||||
|
||||
fLen match {
|
||||
case 32 =>
|
||||
case 64 =>
|
||||
val l2d = Module(new hardfloat.INToRecFN(xLen, dExpWidth, dSigWidth))
|
||||
l2d.io.signedIn := ~in.bits.typ(0)
|
||||
l2d.io.in := intValue
|
||||
l2d.io.roundingMode := in.bits.rm
|
||||
when (!in.bits.single) {
|
||||
mux.data := Cat(UInt((BigInt(1) << (fLen - 64)) - 1), l2d.io.out)
|
||||
mux.exc := l2d.io.exceptionFlags
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
io.out <> Pipe(in.valid, mux, latency-1)
|
||||
}
|
||||
|
||||
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
|
||||
val io = new Bundle {
|
||||
val in = Valid(new FPInput).flip
|
||||
val out = Valid(new FPResult)
|
||||
val lt = Bool(INPUT) // from FPToInt
|
||||
}
|
||||
|
||||
val in = Pipe(io.in)
|
||||
|
||||
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
|
||||
val fsgnj_s = Cat(signNum(32), in.bits.in1(31, 0))
|
||||
val fsgnj = fLen match {
|
||||
case 32 => fsgnj_s
|
||||
case 64 => Mux(in.bits.single, Cat(in.bits.in1 >> 33, fsgnj_s),
|
||||
Cat(signNum(64), in.bits.in1(63, 0)))
|
||||
}
|
||||
val mux = Wire(new FPResult)
|
||||
mux.exc := UInt(0)
|
||||
mux.data := fsgnj
|
||||
|
||||
when (in.bits.cmd === FCMD_MINMAX) {
|
||||
def doMinMax(expWidth: Int, sigWidth: Int) = {
|
||||
val isnan1 = IsNaNRecFN(expWidth, sigWidth, in.bits.in1)
|
||||
val isnan2 = IsNaNRecFN(expWidth, sigWidth, in.bits.in2)
|
||||
val issnan1 = IsSNaNRecFN(expWidth, sigWidth, in.bits.in1)
|
||||
val issnan2 = IsSNaNRecFN(expWidth, sigWidth, in.bits.in2)
|
||||
(isnan2 || in.bits.rm(0) =/= io.lt && !isnan1, issnan1 || issnan2)
|
||||
}
|
||||
val (isLHS, isInvalid) = fLen match {
|
||||
case 32 => doMinMax(sExpWidth, sSigWidth)
|
||||
case 64 => MuxT(in.bits.single, doMinMax(sExpWidth, sSigWidth), doMinMax(dExpWidth, dSigWidth))
|
||||
}
|
||||
mux.exc := isInvalid << 4
|
||||
mux.data := in.bits.in1
|
||||
when (!isLHS) { mux.data := in.bits.in2 }
|
||||
}
|
||||
|
||||
fLen match {
|
||||
case 32 =>
|
||||
case 64 =>
|
||||
when (in.bits.cmd === FCMD_CVT_FF) {
|
||||
when (in.bits.single) {
|
||||
val d2s = Module(new hardfloat.RecFNToRecFN(dExpWidth, dSigWidth, sExpWidth, sSigWidth))
|
||||
d2s.io.in := in.bits.in1
|
||||
d2s.io.roundingMode := in.bits.rm
|
||||
mux.data := Cat(UInt((BigInt(1) << (fLen - 32)) - 1), d2s.io.out)
|
||||
mux.exc := d2s.io.exceptionFlags
|
||||
}.otherwise {
|
||||
val s2d = Module(new hardfloat.RecFNToRecFN(sExpWidth, sSigWidth, dExpWidth, dSigWidth))
|
||||
s2d.io.in := in.bits.in1
|
||||
s2d.io.roundingMode := in.bits.rm
|
||||
mux.data := s2d.io.out
|
||||
mux.exc := s2d.io.exceptionFlags
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
io.out <> Pipe(in.valid, mux, latency-1)
|
||||
}
|
||||
|
||||
class FPToFP(val latency: Int) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val in = Valid(new FPInput).flip
|
||||
val out = Valid(new FPResult)
|
||||
val lt = Bool(INPUT) // from FPToInt
|
||||
}
|
||||
|
||||
val in = Pipe(io.in)
|
||||
|
||||
// fp->fp units
|
||||
val isSgnj = in.bits.cmd === FCMD_SGNJ
|
||||
def fsgnjSign(in1: Bits, in2: Bits, pos: Int, en: Bool, rm: Bits) =
|
||||
Mux(rm(1) || !en, in1(pos), rm(0)) ^ (en && in2(pos))
|
||||
val sign_s = fsgnjSign(in.bits.in1, in.bits.in2, 32, in.bits.single && isSgnj, in.bits.rm)
|
||||
val sign_d = fsgnjSign(in.bits.in1, in.bits.in2, 64, !in.bits.single && isSgnj, in.bits.rm)
|
||||
val fsgnj = Cat(sign_d, in.bits.in1(63,33), sign_s, in.bits.in1(31,0))
|
||||
|
||||
val s2d = Module(new hardfloat.RecFNToRecFN(8, 24, 11, 53))
|
||||
val d2s = Module(new hardfloat.RecFNToRecFN(11, 53, 8, 24))
|
||||
s2d.io.in := in.bits.in1
|
||||
s2d.io.roundingMode := in.bits.rm
|
||||
d2s.io.in := in.bits.in1
|
||||
d2s.io.roundingMode := in.bits.rm
|
||||
|
||||
val isnan1 = Mux(in.bits.single, in.bits.in1(31,29).andR, in.bits.in1(63,61).andR)
|
||||
val isnan2 = Mux(in.bits.single, in.bits.in2(31,29).andR, in.bits.in2(63,61).andR)
|
||||
val issnan1 = isnan1 && ~Mux(in.bits.single, in.bits.in1(22), in.bits.in1(51))
|
||||
val issnan2 = isnan2 && ~Mux(in.bits.single, in.bits.in2(22), in.bits.in2(51))
|
||||
val minmax_exc = Cat(issnan1 || issnan2, Bits(0,4))
|
||||
val isMax = in.bits.rm(0)
|
||||
val isLHS = isnan2 || isMax =/= io.lt && !isnan1
|
||||
|
||||
val mux = Wire(new FPResult)
|
||||
mux.exc := minmax_exc
|
||||
mux.data := in.bits.in2
|
||||
|
||||
when (isSgnj) { mux.exc := UInt(0) }
|
||||
when (isSgnj || isLHS) { mux.data := fsgnj }
|
||||
when (in.bits.cmd === FCMD_CVT_FF) {
|
||||
when (in.bits.single) {
|
||||
mux.data := Cat(SInt(-1, 32), d2s.io.out)
|
||||
mux.exc := d2s.io.exceptionFlags
|
||||
}.otherwise {
|
||||
mux.data := s2d.io.out
|
||||
mux.exc := s2d.io.exceptionFlags
|
||||
}
|
||||
}
|
||||
|
||||
io.out <> Pipe(in.valid, mux, latency-1)
|
||||
}
|
||||
|
||||
class FPUFMAPipe(val latency: Int, expWidth: Int, sigWidth: Int) extends Module
|
||||
{
|
||||
class FPUFMAPipe(val latency: Int, expWidth: Int, sigWidth: Int)(implicit p: Parameters) extends FPUModule()(p) {
|
||||
val io = new Bundle {
|
||||
val in = Valid(new FPInput).flip
|
||||
val out = Valid(new FPResult)
|
||||
@ -412,13 +481,12 @@ class FPUFMAPipe(val latency: Int, expWidth: Int, sigWidth: Int) extends Module
|
||||
fma.io.c := in.in3
|
||||
|
||||
val res = Wire(new FPResult)
|
||||
res.data := Cat(SInt(-1, 32), fma.io.out)
|
||||
res.data := Cat(UInt((BigInt(1) << (fLen - (expWidth + sigWidth))) - 1), fma.io.out)
|
||||
res.exc := fma.io.exceptionFlags
|
||||
io.out := Pipe(valid, res, latency-1)
|
||||
}
|
||||
|
||||
class FPU(cfg: FPUConfig)(implicit p: Parameters) extends CoreModule()(p) {
|
||||
require(xLen == 64, "RV32 Rocket FP support missing")
|
||||
class FPU(cfg: FPUConfig)(implicit p: Parameters) extends FPUModule()(p) {
|
||||
val io = new FPUIO
|
||||
|
||||
val ex_reg_valid = Reg(next=io.valid, init=Bool(false))
|
||||
@ -450,18 +518,20 @@ class FPU(cfg: FPUConfig)(implicit p: Parameters) extends CoreModule()(p) {
|
||||
val load_wb_single = RegEnable(!io.dmem_resp_type(0), io.dmem_resp_val)
|
||||
val load_wb_data = RegEnable(io.dmem_resp_data, io.dmem_resp_val)
|
||||
val load_wb_tag = RegEnable(io.dmem_resp_tag, io.dmem_resp_val)
|
||||
val rec_s = hardfloat.recFNFromFN(8, 24, load_wb_data)
|
||||
val rec_d = hardfloat.recFNFromFN(11, 53, load_wb_data)
|
||||
val load_wb_data_recoded = Mux(load_wb_single, Cat(SInt(-1, 32), rec_s), rec_d)
|
||||
val rec_s = hardfloat.recFNFromFN(sExpWidth, sSigWidth, load_wb_data)
|
||||
val load_wb_data_recoded = fLen match {
|
||||
case 32 => rec_s
|
||||
case 64 =>
|
||||
val rec_d = hardfloat.recFNFromFN(dExpWidth, dSigWidth, load_wb_data)
|
||||
Mux(load_wb_single, Cat(UInt((BigInt(1) << (fLen - 32)) - 1), rec_s), rec_d)
|
||||
}
|
||||
|
||||
// regfile
|
||||
val regfile = Mem(32, Bits(width = 65))
|
||||
val regfile = Mem(32, Bits(width = fLen+1))
|
||||
when (load_wb) {
|
||||
regfile(load_wb_tag) := load_wb_data_recoded
|
||||
if (enableCommitLog) {
|
||||
printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32),
|
||||
Mux(load_wb_single, load_wb_data(31,0), load_wb_data))
|
||||
}
|
||||
if (enableCommitLog)
|
||||
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32, Mux(load_wb_single, load_wb_data(31,0), load_wb_data))
|
||||
}
|
||||
|
||||
val ex_ra1::ex_ra2::ex_ra3::Nil = List.fill(3)(Reg(UInt()))
|
||||
@ -494,14 +564,10 @@ class FPU(cfg: FPUConfig)(implicit p: Parameters) extends CoreModule()(p) {
|
||||
}
|
||||
}
|
||||
|
||||
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, 8, 24))
|
||||
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, sExpWidth, sSigWidth))
|
||||
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.single
|
||||
sfma.io.in.bits := req
|
||||
|
||||
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, 11, 53))
|
||||
dfma.io.in.valid := req_valid && ex_ctrl.fma && !ex_ctrl.single
|
||||
dfma.io.in.bits := req
|
||||
|
||||
val fpiu = Module(new FPToInt)
|
||||
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || ex_ctrl.cmd === FCMD_MINMAX)
|
||||
fpiu.io.in.bits := req
|
||||
@ -512,7 +578,7 @@ class FPU(cfg: FPUConfig)(implicit p: Parameters) extends CoreModule()(p) {
|
||||
io.cp_resp.valid := Bool(true)
|
||||
}
|
||||
|
||||
val ifpu = Module(new IntToFP(3))
|
||||
val ifpu = Module(new IntToFP(2))
|
||||
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
|
||||
ifpu.io.in.bits := req
|
||||
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
|
||||
@ -524,9 +590,9 @@ class FPU(cfg: FPUConfig)(implicit p: Parameters) extends CoreModule()(p) {
|
||||
|
||||
val divSqrt_wen = Reg(next=Bool(false))
|
||||
val divSqrt_inReady = Wire(init=Bool(false))
|
||||
val divSqrt_waddr = Reg(Bits())
|
||||
val divSqrt_wdata = Wire(Bits())
|
||||
val divSqrt_flags = Wire(Bits())
|
||||
val divSqrt_waddr = Reg(UInt(width = 5))
|
||||
val divSqrt_wdata = Wire(UInt(width = fLen+1))
|
||||
val divSqrt_flags = Wire(UInt(width = 5))
|
||||
val divSqrt_in_flight = Reg(init=Bool(false))
|
||||
val divSqrt_killed = Reg(Bool())
|
||||
|
||||
@ -535,8 +601,13 @@ class FPU(cfg: FPUConfig)(implicit p: Parameters) extends CoreModule()(p) {
|
||||
val pipes = List(
|
||||
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
|
||||
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
|
||||
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.single, sfma.io.out.bits),
|
||||
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && !c.single, dfma.io.out.bits))
|
||||
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.single, sfma.io.out.bits)) ++
|
||||
(fLen > 32).option({
|
||||
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, dExpWidth, dSigWidth))
|
||||
dfma.io.in.valid := req_valid && ex_ctrl.fma && !ex_ctrl.single
|
||||
dfma.io.in.bits := req
|
||||
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && !c.single, dfma.io.out.bits)
|
||||
})
|
||||
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
|
||||
require(pipes.forall(_.lat >= offset))
|
||||
pipes.map(p => Mux(p.cond(c), UInt(1 << p.lat-offset), UInt(0))).reduce(_|_)
|
||||
@ -582,10 +653,14 @@ class FPU(cfg: FPUConfig)(implicit p: Parameters) extends CoreModule()(p) {
|
||||
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
|
||||
regfile(waddr) := wdata
|
||||
if (enableCommitLog) {
|
||||
val wdata_unrec_s = hardfloat.fNFromRecFN(8, 24, wdata(64,0))
|
||||
val wdata_unrec_d = hardfloat.fNFromRecFN(11, 53, wdata(64,0))
|
||||
printf ("f%d p%d 0x%x\n", waddr, waddr+ UInt(32),
|
||||
Mux(wbInfo(0).single, Cat(UInt(0,32), wdata_unrec_s), wdata_unrec_d))
|
||||
val wdata_unrec_s = hardfloat.fNFromRecFN(sExpWidth, sSigWidth, wdata)
|
||||
val unrec = fLen match {
|
||||
case 32 => wdata_unrec_s
|
||||
case 64 =>
|
||||
val wdata_unrec_d = hardfloat.fNFromRecFN(dExpWidth, dSigWidth, wdata)
|
||||
Mux(wbInfo(0).single, wdata_unrec_s, wdata_unrec_d)
|
||||
}
|
||||
printf("f%d p%d 0x%x\n", waddr, waddr + 32, unrec)
|
||||
}
|
||||
}
|
||||
when (wbInfo(0).cp && wen(0)) {
|
||||
@ -602,7 +677,7 @@ class FPU(cfg: FPUConfig)(implicit p: Parameters) extends CoreModule()(p) {
|
||||
Mux(divSqrt_wen, divSqrt_flags, UInt(0)) |
|
||||
Mux(wen(0), wexc, UInt(0))
|
||||
|
||||
val units_busy = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && (!divSqrt_inReady || wen.orR) // || mem_reg_valid && mem_ctrl.fma && Reg(next=Mux(ex_ctrl.single, io.sfma.valid, io.dfma.valid))
|
||||
val units_busy = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && (!divSqrt_inReady || wen.orR)
|
||||
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_in_flight)
|
||||
io.nack_mem := units_busy || write_port_busy || divSqrt_in_flight
|
||||
io.dec <> fp_decoder.io.sigs
|
||||
@ -616,6 +691,7 @@ class FPU(cfg: FPUConfig)(implicit p: Parameters) extends CoreModule()(p) {
|
||||
divSqrt_wdata := 0
|
||||
divSqrt_flags := 0
|
||||
if (cfg.divSqrt) {
|
||||
require(fLen == 64)
|
||||
val divSqrt_single = Reg(Bool())
|
||||
val divSqrt_rm = Reg(Bits())
|
||||
val divSqrt_flags_double = Reg(Bits())
|
||||
|
||||
@ -215,73 +215,83 @@ class A64Decode(implicit val p: Parameters) extends DecodeConstants
|
||||
class FDecode(implicit val p: Parameters) extends DecodeConstants
|
||||
{
|
||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||
FCVT_S_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FCVT_D_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSGNJ_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSGNJ_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSGNJX_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSGNJX_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSGNJN_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSGNJN_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FMIN_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FMIN_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FMAX_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FMAX_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FADD_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FADD_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSUB_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSUB_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FMUL_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FMUL_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FMADD_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N),
|
||||
FMADD_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N),
|
||||
FMSUB_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N),
|
||||
FMSUB_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N),
|
||||
FNMADD_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N),
|
||||
FNMADD_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N),
|
||||
FNMSUB_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N),
|
||||
FNMSUB_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N),
|
||||
FCLASS_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FCLASS_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FMV_X_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FCVT_W_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FCVT_W_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FCVT_WU_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FCVT_WU_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FEQ_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N),
|
||||
FEQ_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N),
|
||||
FLT_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N),
|
||||
FLT_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N),
|
||||
FLE_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N),
|
||||
FLE_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N),
|
||||
FMV_S_X-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FCVT_S_W-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FCVT_D_W-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FCVT_S_WU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FCVT_D_WU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FLW-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FLD-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSW-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,Y,N,N,N,N,CSR.N,N,N,N),
|
||||
FSD-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,Y,N,N,N,N,CSR.N,N,N,N))
|
||||
FDIV_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSQRT_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N))
|
||||
}
|
||||
|
||||
class DDecode(implicit val p: Parameters) extends DecodeConstants
|
||||
{
|
||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||
FCVT_S_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FCVT_D_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSGNJ_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSGNJX_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSGNJN_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FMIN_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FMAX_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FADD_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSUB_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FMUL_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FMADD_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N),
|
||||
FMSUB_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N),
|
||||
FNMADD_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N),
|
||||
FNMSUB_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N),
|
||||
FCLASS_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FCVT_W_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FCVT_WU_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FEQ_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N),
|
||||
FLT_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N),
|
||||
FLE_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N),
|
||||
FCVT_D_W-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FCVT_D_WU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FLD-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSD-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,Y,N,N,N,N,CSR.N,N,N,N),
|
||||
FDIV_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSQRT_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N))
|
||||
}
|
||||
|
||||
class F64Decode(implicit val p: Parameters) extends DecodeConstants
|
||||
{
|
||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||
FMV_X_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FCVT_L_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FCVT_L_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FCVT_LU_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FCVT_S_L-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FCVT_S_LU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N))
|
||||
}
|
||||
|
||||
class D64Decode(implicit val p: Parameters) extends DecodeConstants
|
||||
{
|
||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||
FMV_X_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FCVT_L_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FCVT_LU_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N),
|
||||
FMV_D_X-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FCVT_S_L-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FCVT_D_L-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FCVT_S_LU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FCVT_D_LU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N),
|
||||
FDIV_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FDIV_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSQRT_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N),
|
||||
FSQRT_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N))
|
||||
FCVT_D_LU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N))
|
||||
}
|
||||
|
||||
class RoCCDecode(implicit val p: Parameters) extends DecodeConstants
|
||||
|
||||
@ -35,6 +35,7 @@ case object DataScratchpadSize extends Field[Int]
|
||||
trait HasCoreParameters extends HasAddrMapParameters {
|
||||
implicit val p: Parameters
|
||||
val xLen = p(XLen)
|
||||
val fLen = xLen // TODO relax this
|
||||
|
||||
val usingVM = p(UseVM)
|
||||
val usingUser = p(UseUser) || usingVM
|
||||
@ -151,6 +152,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
||||
(if (usingMulDiv) new MDecode +: (xLen > 32).option(new M64Decode).toSeq else Nil) ++:
|
||||
(if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++:
|
||||
(if (usingFPU) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++:
|
||||
(if (usingFPU && xLen > 32) Seq(new DDecode, new D64Decode) else Nil) ++:
|
||||
(usingRoCC.option(new RoCCDecode)) ++:
|
||||
((xLen > 32).option(new I64Decode)) ++:
|
||||
(usingVM.option(new SDecode)) ++:
|
||||
|
||||
@ -30,10 +30,18 @@ object Util {
|
||||
def toInt: Int = if (x) 1 else 0
|
||||
|
||||
// this one's snagged from scalaz
|
||||
def option[T](z: T): Option[T] = if (x) Some(z) else None
|
||||
def option[T](z: => T): Option[T] = if (x) Some(z) else None
|
||||
}
|
||||
}
|
||||
|
||||
object MuxT {
|
||||
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
|
||||
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
|
||||
|
||||
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
|
||||
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
|
||||
}
|
||||
|
||||
import Util._
|
||||
|
||||
object Str
|
||||
|
||||
@ -35,7 +35,7 @@ class BasePlatformConfig extends Config (
|
||||
new AddrMap(entries)
|
||||
}
|
||||
lazy val externalAddrMap = new AddrMap(
|
||||
site(ExtIOAddrMapEntries),
|
||||
site(ExtraDevices).addrMapEntries ++ site(ExtMMIOPorts),
|
||||
start = BigInt("50000000", 16),
|
||||
collapse = true)
|
||||
lazy val globalAddrMap = {
|
||||
@ -73,10 +73,17 @@ class BasePlatformConfig extends Config (
|
||||
res append s" size 0x${addrMap("mem").size.toString(16)};\n"
|
||||
res append " };\n"
|
||||
res append "};\n"
|
||||
res append "core {\n"
|
||||
}
|
||||
res append "core {\n"
|
||||
for (i <- 0 until site(NTiles)) { // TODO heterogeneous tiles
|
||||
val isa = s"rv${site(XLen)}i${site(MulDivKey).map(x=>"m").mkString}${if (site(UseAtomics)) "a" else ""}${if (site(FPUKey).nonEmpty) "fd" else ""}"
|
||||
val isa = {
|
||||
val m = if (site(MulDivKey).nonEmpty) "m" else ""
|
||||
val a = if (site(UseAtomics)) "a" else ""
|
||||
val f = if (site(FPUKey).nonEmpty) "f" else ""
|
||||
val d = if (site(FPUKey).nonEmpty && site(XLen) > 32) "d" else ""
|
||||
val s = if (site(UseVM)) "s" else ""
|
||||
s"rv${site(XLen)}i$m$a$f$d$s"
|
||||
}
|
||||
res append s" $i {\n"
|
||||
res append " 0 {\n"
|
||||
res append s" isa $isa;\n"
|
||||
@ -95,7 +102,7 @@ class BasePlatformConfig extends Config (
|
||||
res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'S')).toString(16)};\n"
|
||||
res append s" };\n"
|
||||
}
|
||||
res append s" };\n"
|
||||
res append " };\n"
|
||||
res append " };\n"
|
||||
res append " };\n"
|
||||
}
|
||||
@ -131,12 +138,10 @@ class BasePlatformConfig extends Config (
|
||||
case ExtraDevices => new EmptyDeviceBlock
|
||||
case ExtraTopPorts => (p: Parameters) => new Bundle
|
||||
case ExtMMIOPorts => Nil
|
||||
case ExtIOAddrMapEntries =>
|
||||
site(ExtraDevices).addrMapEntries ++ site(ExtMMIOPorts)
|
||||
case NExtMMIOAXIChannels => 0
|
||||
case NExtMMIOAHBChannels => 0
|
||||
case NExtMMIOTLChannels => 0
|
||||
case ExportMMIOPort => site(ExtIOAddrMapEntries).size > 0
|
||||
case ExportMMIOPort => !externalAddrMap.isEmpty
|
||||
case AsyncBusChannels => false
|
||||
case NExtBusAXIChannels => 0
|
||||
case NExternalClients => (if (site(NExtBusAXIChannels) > 0) 1 else 0) +
|
||||
@ -214,7 +219,7 @@ class WithScratchpads extends Config(new WithNMemoryChannels(0) ++ new WithDataS
|
||||
|
||||
class DefaultFPGASmallConfig extends Config(new WithSmallCores ++ new DefaultFPGAConfig)
|
||||
class DefaultSmallConfig extends Config(new WithSmallCores ++ new BaseConfig)
|
||||
class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultSmallConfig)
|
||||
class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultConfig)
|
||||
|
||||
class DualBankConfig extends Config(
|
||||
new WithNBanksPerMemChannel(2) ++ new BaseConfig)
|
||||
@ -262,7 +267,7 @@ class DualCoreConfig extends Config(
|
||||
|
||||
class TinyConfig extends Config(
|
||||
new WithScratchpads ++
|
||||
new WithRV32 ++ new WithSmallCores ++
|
||||
new WithSmallCores ++ new WithRV32 ++
|
||||
new WithStatelessBridge ++ new BaseConfig)
|
||||
|
||||
class WithTestRAM extends Config(
|
||||
|
||||
@ -41,7 +41,6 @@ case object AsyncMemChannels extends Field[Boolean]
|
||||
case object AsyncMMIOChannels extends Field[Boolean]
|
||||
/** External address map settings */
|
||||
case object ExtMMIOPorts extends Field[Seq[AddrMapEntry]]
|
||||
case object ExtIOAddrMapEntries extends Field[Seq[AddrMapEntry]]
|
||||
/** Function for building Coreplex */
|
||||
case object BuildCoreplex extends Field[Parameters => Coreplex]
|
||||
/** Function for connecting coreplex extra ports to top-level extra ports */
|
||||
|
||||
@ -51,7 +51,7 @@ case class PLICConfig(nHartsIn: Int, supervisor: Boolean, nDevices: Int, nPriori
|
||||
def claimOffset = 4
|
||||
def priorityBytes = 4
|
||||
|
||||
require(nDevices > 0 && nDevices <= maxDevices)
|
||||
require(nDevices <= maxDevices)
|
||||
require(nHarts > 0 && nHarts <= maxHarts)
|
||||
require(nPriorities >= 0 && nPriorities <= nDevices)
|
||||
}
|
||||
@ -117,7 +117,7 @@ class PLIC(val cfg: PLICConfig)(implicit val p: Parameters) extends Module
|
||||
val rdata = Wire(init = UInt(0, tlDataBits))
|
||||
val masked_wdata = (acq.bits.data & acq.bits.full_wmask()) | (rdata & ~acq.bits.full_wmask())
|
||||
|
||||
when (addr >= cfg.hartBase) {
|
||||
if (cfg.nDevices > 0) when (addr >= cfg.hartBase) {
|
||||
val word =
|
||||
if (tlDataBytes > cfg.claimOffset) UInt(0)
|
||||
else addr(log2Up(cfg.claimOffset),log2Up(tlDataBytes))
|
||||
|
||||
@ -11,7 +11,8 @@ default: all
|
||||
|
||||
base_dir = $(abspath ..)
|
||||
generated_dir = $(abspath ./generated-src)
|
||||
mem_gen = $(base_dir)/vsim/vlsi_mem_gen
|
||||
VLSI_MEM_GEN ?= $(base_dir)/vsim/vlsi_mem_gen
|
||||
mem_gen = $(VLSI_MEM_GEN)
|
||||
sim_dir = .
|
||||
output_dir = $(sim_dir)/output
|
||||
|
||||
|
||||
@ -10,6 +10,7 @@ bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
|
||||
|
||||
sim_vsrcs = \
|
||||
$(generated_dir)/$(MODEL).$(CONFIG).v \
|
||||
$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v \
|
||||
$(generated_dir)/consts.$(CONFIG).vh \
|
||||
$(base_dir)/vsrc/$(TB).v \
|
||||
$(base_dir)/vsrc/SimDTM.v \
|
||||
|
||||
@ -9,9 +9,15 @@ $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)
|
||||
mkdir -p $(dir $@)
|
||||
cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(CFG_PROJECT) $(CONFIG)"
|
||||
|
||||
$(generated_dir)/%.v: $(generated_dir)/%.fir $(FIRRTL_JAR)
|
||||
$(generated_dir)/%.v $(generated_dir)/%.conf : $(generated_dir)/%.fir $(FIRRTL_JAR)
|
||||
mkdir -p $(dir $@)
|
||||
$(FIRRTL) -i $< -o $@ -X verilog
|
||||
$(FIRRTL) -i $< -o $@ -X verilog --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(MODEL).$(CONFIG).conf
|
||||
|
||||
$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v : $(generated_dir)/$(MODEL).$(CONFIG).conf $(mem_gen)
|
||||
cd $(generated_dir) && \
|
||||
rm -f $@ && \
|
||||
$(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $@.tmp && \
|
||||
mv $@.tmp $@
|
||||
|
||||
$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).prm
|
||||
echo "\`ifndef CONST_VH" > $@
|
||||
|
||||
@ -12,7 +12,7 @@ def parse_line(line):
|
||||
width = 0
|
||||
depth = 0
|
||||
ports = ''
|
||||
mask_gran = 1
|
||||
mask_gran = 0
|
||||
tokens = line.split()
|
||||
i = 0
|
||||
for i in range(0,len(tokens),2):
|
||||
@ -21,20 +21,20 @@ def parse_line(line):
|
||||
name = tokens[i+1]
|
||||
elif s == 'width':
|
||||
width = int(tokens[i+1])
|
||||
mask_gran = width # default setting
|
||||
elif s == 'depth':
|
||||
depth = int(tokens[i+1])
|
||||
elif s == 'ports':
|
||||
ports = tokens[i+1].split(',')
|
||||
elif s == 'mask_gran':
|
||||
# currently used only for fpga, but here for .conf format compatability
|
||||
mask_gran = int(tokens[i+1])
|
||||
else:
|
||||
sys.exit('%s: unknown argument %s' % (sys.argv[0], a))
|
||||
return (name, width, depth, ports)
|
||||
return (name, width, depth, mask_gran, width/mask_gran, ports)
|
||||
|
||||
def gen_mem(name, width, depth, ports):
|
||||
def gen_mem(name, width, depth, mask_gran, mask_seg, ports):
|
||||
addr_width = max(math.ceil(math.log(depth)/math.log(2)),1)
|
||||
port_spec = ['input CLK', 'input RST', 'input init']
|
||||
port_spec = []
|
||||
readports = []
|
||||
writeports = []
|
||||
latchports = []
|
||||
@ -50,28 +50,34 @@ def gen_mem(name, width, depth, ports):
|
||||
maskedports[pid] = pid
|
||||
|
||||
if ptype == 'read':
|
||||
port_spec.append('input [%d:0] R%dA' % (addr_width-1, pid))
|
||||
port_spec.append('input R%dE' % pid)
|
||||
port_spec.append('output [%d:0] R%dO' % (width-1, pid))
|
||||
prefix = 'R%d_' % len(readports)
|
||||
port_spec.append('input %sclk' % prefix)
|
||||
port_spec.append('input [%d:0] %saddr' % (addr_width-1, prefix))
|
||||
port_spec.append('input %sen' % prefix)
|
||||
port_spec.append('output [%d:0] %sdata' % (width-1, prefix))
|
||||
readports.append(pid)
|
||||
elif ptype == 'write':
|
||||
port_spec.append('input [%d:0] W%dA' % (addr_width-1, pid))
|
||||
port_spec.append('input W%dE' % pid)
|
||||
port_spec.append('input [%d:0] W%dI' % (width-1, pid))
|
||||
prefix = 'W%d_' % len(writeports)
|
||||
port_spec.append('input %sclk' % prefix)
|
||||
port_spec.append('input [%d:0] %saddr' % (addr_width-1, prefix))
|
||||
port_spec.append('input %sen' % prefix)
|
||||
port_spec.append('input [%d:0] %sdata' % (width-1, prefix))
|
||||
if pid in maskedports:
|
||||
port_spec.append('input [%d:0] W%dM' % (width-1, pid))
|
||||
port_spec.append('input [%d:0] %smask' % (mask_seg-1, prefix))
|
||||
if not use_latches or pid in maskedports:
|
||||
writeports.append(pid)
|
||||
else:
|
||||
latchports.append(pid)
|
||||
elif ptype == 'rw':
|
||||
port_spec.append('input [%d:0] RW%dA' % (addr_width-1, pid))
|
||||
port_spec.append('input RW%dE' % pid)
|
||||
port_spec.append('input RW%dW' % pid)
|
||||
prefix = 'RW%d_' % len(rwports)
|
||||
port_spec.append('input %sclk' % prefix)
|
||||
port_spec.append('input [%d:0] %saddr' % (addr_width-1, prefix))
|
||||
port_spec.append('input %sen' % prefix)
|
||||
port_spec.append('input %swmode' % prefix)
|
||||
if pid in maskedports:
|
||||
port_spec.append('input [%d:0] RW%dM' % (width-1, pid))
|
||||
port_spec.append('input [%d:0] RW%dI' % (width-1, pid))
|
||||
port_spec.append('output [%d:0] RW%dO' % (width-1, pid))
|
||||
port_spec.append('input [%d:0] %swmask' % (mask_seg-1, prefix))
|
||||
port_spec.append('input [%d:0] %swdata' % (width-1, prefix))
|
||||
port_spec.append('output [%d:0] %srdata' % (width-1, prefix))
|
||||
rwports.append(pid)
|
||||
else:
|
||||
sys.exit('%s: unknown port type %s' % (sys.argv[0], ptype))
|
||||
@ -82,66 +88,83 @@ def gen_mem(name, width, depth, ports):
|
||||
masked = len(maskedports)>0
|
||||
tup = (depth, width, nr, nw, nrw, masked)
|
||||
|
||||
for pid in readports:
|
||||
decl.append('reg [%d:0] reg_R%dA;' % (addr_width-1, pid))
|
||||
sequential.append('if (R%dE) reg_R%dA <= R%dA;' % (pid, pid, pid))
|
||||
combinational.append('assign R%dO = ram[reg_R%dA];' % (pid, pid))
|
||||
for idx in range(nr):
|
||||
prefix = 'R%d_' % idx
|
||||
decl.append('reg [%d:0] reg_%saddr;' % (addr_width-1, prefix))
|
||||
sequential.append('always @(posedge %sclk)' % prefix)
|
||||
sequential.append(' if (%sen) reg_%saddr <= %saddr;' % (prefix, prefix, prefix))
|
||||
combinational.append('assign %sdata = ram[reg_%saddr];' % (prefix, prefix))
|
||||
|
||||
for pid in rwports:
|
||||
decl.append('reg [%d:0] reg_RW%dA;' % (addr_width-1, pid))
|
||||
sequential.append('if (RW%dE && !RW%dW) reg_RW%dA <= RW%dA;' % (pid, pid, pid, pid))
|
||||
combinational.append('assign RW%dO = ram[reg_RW%dA];' % (pid, pid))
|
||||
for idx in range(nrw):
|
||||
prefix = 'RW%d_' % idx
|
||||
decl.append('reg [%d:0] reg_%saddr;' % (addr_width-1, prefix))
|
||||
sequential.append('always @(posedge %sclk)' % prefix)
|
||||
sequential.append(' if (%sen && !%swmode) reg_%saddr <= %saddr;' % (prefix, prefix, prefix, prefix))
|
||||
combinational.append('assign %srdata = ram[reg_%saddr];' % (prefix, prefix))
|
||||
|
||||
for pid in latchports:
|
||||
decl.append('reg [%d:0] latch_W%dA;' % (addr_width-1, pid))
|
||||
decl.append('reg [%d:0] latch_W%dI;' % (width-1, pid))
|
||||
decl.append('reg latch_W%dE;' % (pid))
|
||||
for idx in range(len(latchports)):
|
||||
prefix = 'W%d_' % idx
|
||||
decl.append('reg [%d:0] latch_%saddr;' % (addr_width-1, prefix))
|
||||
decl.append('reg [%d:0] latch_%sdata;' % (width-1, prefix))
|
||||
decl.append('reg latch_%sen;' % (prefix))
|
||||
combinational.append('always @(*) begin')
|
||||
combinational.append(' if (!CLK && W%dE) latch_W%dA <= W%dA;' % (pid, pid, pid))
|
||||
combinational.append(' if (!CLK && W%dE) latch_W%dI <= W%dI;' % (pid, pid, pid))
|
||||
combinational.append(' if (!CLK) latch_W%dE <= W%dE;' % (pid, pid))
|
||||
combinational.append(' if (!%sclk && %sen) latch_%saddr <= %saddr;' % (prefix, prefix, prefix, prefix))
|
||||
combinational.append(' if (!%sclk && %sen) latch_%sdata <= %sdata;' % (prefix, prefix, prefix, prefix))
|
||||
combinational.append(' if (!%sclk) latch_%sen <= %sen;' % (prefix, prefix, prefix))
|
||||
combinational.append('end')
|
||||
combinational.append('always @(*)')
|
||||
combinational.append(' if (CLK && latch_W%dE)' % (pid))
|
||||
combinational.append(' ram[latch_W%dA] <= latch_W%dI;' % (pid, pid))
|
||||
combinational.append(' if (%sclk && latch_%sen)' % (prefix, prefix))
|
||||
combinational.append(' ram[latch_%saddr] <= latch_%sdata;' % (prefix, prefix))
|
||||
|
||||
decl.append('reg [%d:0] ram [%d:0];' % (width-1, depth-1))
|
||||
decl.append('`ifndef SYNTHESIS')
|
||||
decl.append('`ifdef RANDOMIZE')
|
||||
decl.append(' integer initvar;')
|
||||
decl.append(' initial begin')
|
||||
decl.append(' #0.002;')
|
||||
decl.append(' #0.002 begin end')
|
||||
decl.append(' for (initvar = 0; initvar < %d; initvar = initvar+1)' % depth)
|
||||
decl.append(' ram[initvar] = {%d {$random}};' % ((width-1)/32+1))
|
||||
for pid in readports:
|
||||
decl.append(' reg_R%dA = {%d {$random}};' % (pid, ((addr_width-1)/32+1)))
|
||||
for pid in rwports:
|
||||
decl.append(' reg_RW%dA = {%d {$random}};' % (pid, ((addr_width-1)/32+1)))
|
||||
for idx in range(nr):
|
||||
prefix = 'R%d_' % idx
|
||||
decl.append(' reg_%saddr = {%d {$random}};' % (prefix, ((addr_width-1)/32+1)))
|
||||
for idx in range(nrw):
|
||||
prefix = 'RW%d_' % idx
|
||||
decl.append(' reg_%saddr = {%d {$random}};' % (prefix, ((addr_width-1)/32+1)))
|
||||
decl.append(' end')
|
||||
decl.append('`endif')
|
||||
|
||||
decl.append("integer i;")
|
||||
sequential.append("for (i = 0; i < %d; i=i+1) begin" % width)
|
||||
for pid in writeports:
|
||||
mask = (' && W%dM[i]' % pid) if pid in maskedports else ''
|
||||
sequential.append(" if (W%dE%s) ram[W%dA][i] <= W%dI[i];" % (pid, mask, pid, pid))
|
||||
for pid in rwports:
|
||||
mask = (' && RW%dM[i]' % pid) if pid in maskedports else ''
|
||||
sequential.append(" if (RW%dE && RW%dW%s) ram[RW%dA][i] <= RW%dI[i];" % (pid, pid, mask, pid, pid))
|
||||
sequential.append("end")
|
||||
for idx in range(nw):
|
||||
prefix = 'W%d_' % idx
|
||||
pid = writeports[idx]
|
||||
sequential.append('always @(posedge %sclk)' % prefix)
|
||||
sequential.append(" if (%sen) begin" % prefix)
|
||||
for i in range(mask_seg):
|
||||
mask = ('if (%smask[%d]) ' % (prefix, i)) if pid in maskedports else ''
|
||||
ram_range = '%d:%d' % ((i+1)*mask_gran-1, i*mask_gran)
|
||||
sequential.append(" %sram[%saddr][%s] <= %sdata[%s];" % (mask, prefix, ram_range, prefix, ram_range))
|
||||
sequential.append(" end")
|
||||
for idx in range(nrw):
|
||||
pid = rwports[idx]
|
||||
prefix = 'RW%d_' % idx
|
||||
sequential.append('always @(posedge %sclk)' % prefix)
|
||||
sequential.append(" if (%sen && %swmode) begin" % (prefix, prefix))
|
||||
for i in range(mask_seg):
|
||||
mask = ('if (%swmask[%d]) ' % (prefix, i)) if pid in maskedports else ''
|
||||
ram_range = '%d:%d' % ((i+1)*mask_gran-1, i*mask_gran)
|
||||
sequential.append(" %sram[%saddr][%s] <= %swdata[%s];" % (mask, prefix, ram_range, prefix, ram_range))
|
||||
sequential.append(" end")
|
||||
body = "\
|
||||
%s\n\
|
||||
always @(posedge CLK) begin\n\
|
||||
%s\n\
|
||||
end\n\
|
||||
%s\n" % ('\n '.join(decl), '\n '.join(sequential), '\n '.join(combinational))
|
||||
%s\n\
|
||||
%s\n" % ('\n '.join(decl), '\n '.join(sequential), '\n '.join(combinational))
|
||||
|
||||
s = "module %s(\n\
|
||||
s = "\nmodule %s(\n\
|
||||
%s\n\
|
||||
);\n\
|
||||
\n\
|
||||
%s\
|
||||
\n\
|
||||
endmodule\n" % (name, ',\n '.join(port_spec), body)
|
||||
endmodule" % (name, ',\n '.join(port_spec), body)
|
||||
return s
|
||||
|
||||
def main():
|
||||
|
||||
Loading…
Reference in New Issue
Block a user