From 22ffe36258c745776f7632de717d79f8a35f79ba Mon Sep 17 00:00:00 2001 From: mwachs5 Date: Fri, 19 Aug 2016 22:51:49 -0700 Subject: [PATCH] Add a queue for timing QoR between L2->MMIO network (#217) --- src/main/scala/coreplex/Coreplex.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala index 7ec15395..8599205e 100644 --- a/src/main/scala/coreplex/Coreplex.scala +++ b/src/main/scala/coreplex/Coreplex.scala @@ -193,7 +193,9 @@ class DefaultOuterMemorySystem(implicit p: Parameters) extends OuterMemorySystem case InnerTLId => "L1toL2" case OuterTLId => "L2toMMIO" }))) - io.mmio <> mmioManager.io.outer + + io.mmio.acquire <> Queue(mmioManager.io.outer.acquire, 1) + mmioManager.io.outer.grant <> Queue(io.mmio.grant, 1) // Wire the tiles to the TileLink client ports of the L1toL2 network, // and coherence manager(s) to the other side