riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

fix typo causing L2 cache configuration to fail

Browse Source
This commit is contained in:
Howard Mao 2015-10-21 13:37:33 -07:00
parent d5a75fd113
commit 21f342ad42
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
uncore

@ -1 +1 @@
Subproject commit 758a5eeb2322cc7c36c1ad4a98e57a5b3ab2b707
Subproject commit ce01a9bbf02fa982d1c2520a595f3e2427662846