riscv/rocket-chip
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fix typo causing L2 cache configuration to fail

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Howard Mao 2015-10-21 13:37:33 -07:00
parent d5a75fd113
commit 21f342ad42
1 changed files with 1 additions and 1 deletions
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uncore

@ -1 +1 @@
Subproject commit 758a5eeb2322cc7c36c1ad4a98e57a5b3ab2b707 Subproject commit ce01a9bbf02fa982d1c2520a595f3e2427662846