riscv/rocket-chip
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Don't build verilog twice for emulator and emulator-debug

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Since we aren't using chisel2, the output is the same either way.
This commit is contained in:
Andrew Waterman 2017-08-04 01:01:15 -07:00
parent 017ac130c1
commit 21ac28b57a
1 changed files with 2 additions and 8 deletions
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10
emulator/Makefrag-verilator
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@ -2,20 +2,14 @@
# Verilator Generation # Verilator Generation
#-------------------------------------------------------------------- #--------------------------------------------------------------------
firrtl = $(generated_dir)/$(long_name).fir firrtl = $(generated_dir)/$(long_name).fir
firrtl_debug = $(generated_dir_debug)/$(long_name).fir
verilog = $(generated_dir)/$(long_name).v verilog = $(generated_dir)/$(long_name).v
verilog_debug = $(generated_dir_debug)/$(long_name).v
.SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug) .SECONDARY: $(firrtl) $(verilog)
$(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img) $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@) mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
$(generated_dir_debug)/%.fir $(generated_dir_debug)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir_debug) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
%.v: %.fir $(FIRRTL_JAR) %.v: %.fir $(FIRRTL_JAR)
mkdir -p $(dir $@) mkdir -p $(dir $@)
$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog $(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog
@ -72,7 +66,7 @@ $(emu): $(verilog) $(cppfiles) $(headers) $(INSTALLED_VERILATOR)
-CFLAGS "-I$(generated_dir) -include $(model_header)" -CFLAGS "-I$(generated_dir) -include $(model_header)"
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir)/$(long_name) -f V$(MODEL).mk $(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir)/$(long_name) -f V$(MODEL).mk
$(emu_debug): $(verilog_debug) $(cppfiles) $(headers) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR) $(emu_debug): $(verilog) $(cppfiles) $(headers) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir_debug)/$(long_name) mkdir -p $(generated_dir_debug)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(long_name) --trace \ $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(long_name) --trace \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \ -o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \