tileink: FIFOFixer should cope with zero-latency devices
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@ -74,8 +74,8 @@ class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Para
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// Keep one bit for each source recording if there is an outstanding request that must be made FIFO
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// Sources unused in the stall signal calculation should be pruned by DCE
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val flight = RegInit(Vec.fill(edgeIn.client.endSourceId) { Bool(false) })
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when (d_first && in.d.fire()) { flight(in.d.bits.source) := Bool(false) }
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when (a_first && in.a.fire()) { flight(in.a.bits.source) := !a_notFIFO }
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when (d_first && in.d.fire()) { flight(in.d.bits.source) := Bool(false) }
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val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c =>
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val a_sel = c.sourceId.contains(in.a.bits.source)
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