riscv/rocket-chip
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vsrc: add ClockDivider3 used to simulate unaligned clocks

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Wesley W. Terpstra committed 2017-05-14 15:05:55 -07:00
1 parent 05e7501e7a
commit 2119df5a60
3 files changed
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vsim/Makefrag
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@@ -7,6 +7,7 @@
bb_vsrcs = \
$(base_dir)/vsrc/jtag_vpi.v \
$(base_dir)/vsrc/ClockDivider2.v \
$(base_dir)/vsrc/ClockDivider3.v \
$(base_dir)/vsrc/AsyncResetReg.v \
sim_vsrcs = \