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tilelink2: reuse the halves of the AsyncQueue

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This commit is contained in:
Wesley W. Terpstra
2016-09-29 17:12:13 -07:00
parent 8e4c1e567c
commit 20f42a8762
2 changed files with 42 additions and 8 deletions
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15
src/main/scala/util/AsyncQueue.scala
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@@ -25,8 +25,7 @@ object AsyncGrayCounter {
}
}
class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int, clockIn: Clock, resetIn: Bool)
extends Module(_clock = clockIn, _reset = resetIn) {
class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int) extends Module {
val bits = log2Ceil(depth)
val io = new Bundle {
// These come from the source domain
@@ -53,8 +52,7 @@ class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int, clockIn: Clock,
io.mem := mem
}
class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int, clockIn: Clock, resetIn: Bool)
extends Module(_clock = clockIn, _reset = resetIn) {
class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int) extends Module {
val bits = log2Ceil(depth)
val io = new Bundle {
// These come from the sink domain
@@ -88,8 +86,13 @@ class AsyncQueue[T <: Data](gen: T, depth: Int = 8, sync: Int = 3) extends Cross
require (depth > 0 && isPow2(depth))
val io = new CrossingIO(gen)
val source = Module(new AsyncQueueSource(gen, depth, sync, io.enq_clock, io.enq_reset))
val sink = Module(new AsyncQueueSink (gen, depth, sync, io.deq_clock, io.deq_reset))
val source = Module(new AsyncQueueSource(gen, depth, sync))
val sink = Module(new AsyncQueueSink (gen, depth, sync))
source.clock := io.enq_clock
source.reset := io.enq_reset
sink.clock := io.deq_clock
sink.reset := io.deq_reset
source.io.enq <> io.enq
io.deq <> sink.io.deq