riscv/rocket-chip
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move PCR writes to WB stage

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This commit is contained in:
Andrew Waterman 2012-01-02 15:42:39 -08:00
parent 3045b33460
commit 20aee36c96
4 changed files with 56 additions and 15 deletions
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36
rocket/src/main/scala/ctrl.scala
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@ -34,7 +34,7 @@ class ioCtrlDpath extends Bundle()
val ren_pcr = Bool('output); val ren_pcr = Bool('output);
val wen_pcr = Bool('output); val wen_pcr = Bool('output);
val id_eret = Bool('output); val id_eret = Bool('output);
val mem_eret = Bool('output); val wb_eret = Bool('output);
val mem_load = Bool('output); val mem_load = Bool('output);
val wen = Bool('output); val wen = Bool('output);
// instruction in execute is an unconditional jump // instruction in execute is an unconditional jump
@ -357,6 +357,13 @@ class rocketCtrl extends Component
val mem_reg_replay = Reg(resetVal = Bool(false)); val mem_reg_replay = Reg(resetVal = Bool(false));
val mem_reg_kill_dmem = Reg(resetVal = Bool(false)); val mem_reg_kill_dmem = Reg(resetVal = Bool(false));
val wb_reg_inst_di = Reg(resetVal = Bool(false));
val wb_reg_inst_ei = Reg(resetVal = Bool(false));
val wb_reg_eret = Reg(resetVal = Bool(false));
val wb_reg_exception = Reg(resetVal = Bool(false));
val wb_reg_badvaddr_wen = Reg(resetVal = Bool(false));
val wb_reg_cause = Reg(){UFix()};
when (!io.dpath.stalld) { when (!io.dpath.stalld) {
when (io.dpath.killf) { when (io.dpath.killf) {
id_reg_xcpt_ma_inst <== Bool(false); id_reg_xcpt_ma_inst <== Bool(false);
@ -478,6 +485,17 @@ class rocketCtrl extends Component
mem_reg_xcpt_syscall <== ex_reg_xcpt_syscall; mem_reg_xcpt_syscall <== ex_reg_xcpt_syscall;
} }
when (io.dpath.killm) {
wb_reg_eret <== Bool(false);
wb_reg_inst_di <== Bool(false);
wb_reg_inst_ei <== Bool(false);
}
otherwise {
wb_reg_eret <== mem_reg_eret;
wb_reg_inst_di <== mem_reg_inst_di;
wb_reg_inst_ei <== mem_reg_inst_ei;
}
wb_reg_div_mul_val <== mem_reg_div_mul_val; wb_reg_div_mul_val <== mem_reg_div_mul_val;
// exception handling // exception handling
@ -524,10 +542,14 @@ class rocketCtrl extends Component
Mux(io.xcpt_dtlb_st, UFix(11,5), // store fault Mux(io.xcpt_dtlb_st, UFix(11,5), // store fault
UFix(0,5))))))))))); // instruction address misaligned UFix(0,5))))))))))); // instruction address misaligned
wb_reg_exception <== mem_exception;
wb_reg_badvaddr_wen <== io.xcpt_dtlb_ld || io.xcpt_dtlb_st;
wb_reg_cause <== mem_cause;
// write cause to PCR on an exception // write cause to PCR on an exception
io.dpath.exception := mem_exception; io.dpath.exception := wb_reg_exception;
io.dpath.cause := mem_cause; io.dpath.cause := wb_reg_cause;
io.dpath.badvaddr_wen := io.xcpt_dtlb_ld || io.xcpt_dtlb_st; io.dpath.badvaddr_wen := wb_reg_badvaddr_wen;
// replay mem stage PC on a DTLB miss // replay mem stage PC on a DTLB miss
val mem_hazard = io.dtlb_miss || io.dmem.resp_nack; val mem_hazard = io.dtlb_miss || io.dmem.resp_nack;
@ -662,9 +684,9 @@ class rocketCtrl extends Component
io.dpath.ren_pcr := id_ren_pcr.toBool; io.dpath.ren_pcr := id_ren_pcr.toBool;
io.dpath.wen_pcr := id_wen_pcr.toBool; io.dpath.wen_pcr := id_wen_pcr.toBool;
io.dpath.id_eret := id_eret.toBool; io.dpath.id_eret := id_eret.toBool;
io.dpath.mem_eret := mem_reg_eret; io.dpath.wb_eret := wb_reg_eret;
io.dpath.irq_disable := mem_reg_inst_di && !kill_mem; io.dpath.irq_disable := wb_reg_inst_di;
io.dpath.irq_enable := mem_reg_inst_ei && !kill_mem; io.dpath.irq_enable := wb_reg_inst_ei;
io.dtlb_val := ex_reg_mem_val && !ex_kill_dtlb; io.dtlb_val := ex_reg_mem_val && !ex_kill_dtlb;
io.dmem.req_val := ex_reg_mem_val; io.dmem.req_val := ex_reg_mem_val;

5
rocket/src/main/scala/divider.scala
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@ -7,6 +7,7 @@ import Constants._;
class ioDivider(width: Int) extends Bundle { class ioDivider(width: Int) extends Bundle {
// requests // requests
val div_val = Bool('input); val div_val = Bool('input);
val div_kill = Bool('input);
val div_rdy = Bool('output); val div_rdy = Bool('output);
val dw = UFix(1, 'input); val dw = UFix(1, 'input);
val div_fn = UFix(2, 'input); val div_fn = UFix(2, 'input);
@ -55,6 +56,10 @@ class rocketDivider(width : Int) extends Component {
val tc = (io.div_fn === DIV_D) || (io.div_fn === DIV_R); val tc = (io.div_fn === DIV_D) || (io.div_fn === DIV_R);
when (io.div_kill) {
state <== s_ready;
}
// state machine // state machine
switch (state) { switch (state) {
is (s_ready) { is (s_ready) {

27
rocket/src/main/scala/dpath.scala
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@ -105,14 +105,19 @@ class rocketDpath extends Component
val mem_reg_wdata = Reg() { Bits() }; val mem_reg_wdata = Reg() { Bits() };
val mem_reg_raddr2 = Reg() { UFix() }; val mem_reg_raddr2 = Reg() { UFix() };
val mem_reg_ctrl_ll_wb = Reg(resetVal = Bool(false)); val mem_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
val mem_reg_ctrl_mul_val = Reg(resetVal = Bool(false));
val mem_reg_ctrl_div_val = Reg(resetVal = Bool(false));
val mem_reg_ctrl_wen = Reg(resetVal = Bool(false)); val mem_reg_ctrl_wen = Reg(resetVal = Bool(false));
val mem_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false)); val mem_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
// writeback definitions // writeback definitions
val wb_reg_pc = Reg() { UFix() };
val wb_reg_waddr = Reg() { UFix() }; val wb_reg_waddr = Reg() { UFix() };
val wb_reg_wdata = Reg() { Bits() }; val wb_reg_wdata = Reg() { Bits() };
val wb_reg_raddr2 = Reg() { UFix() };
val wb_reg_ctrl_ll_wb = Reg(resetVal = Bool(false)); val wb_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
val wb_reg_ctrl_wen = Reg(resetVal = Bool(false)); val wb_reg_ctrl_wen = Reg(resetVal = Bool(false));
val wb_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
val r_dmem_resp_val = Reg(resetVal = Bool(false)); val r_dmem_resp_val = Reg(resetVal = Bool(false));
val r_dmem_resp_replay = Reg(resetVal = Bool(false)); val r_dmem_resp_replay = Reg(resetVal = Bool(false));
@ -280,7 +285,8 @@ class rocketDpath extends Component
// divider // divider
div.io.dw := ex_reg_ctrl_fn_dw; div.io.dw := ex_reg_ctrl_fn_dw;
div.io.div_fn := ex_reg_ctrl_div_fn; div.io.div_fn := ex_reg_ctrl_div_fn;
div.io.div_val := ex_reg_ctrl_div_val && !io.ctrl.killx; div.io.div_val := ex_reg_ctrl_div_val;
div.io.div_kill := mem_reg_ctrl_div_val && io.ctrl.killm;
div.io.div_waddr := ex_reg_waddr; div.io.div_waddr := ex_reg_waddr;
div.io.dpath_rs1 := ex_reg_rs1; div.io.dpath_rs1 := ex_reg_rs1;
div.io.dpath_rs2 := ex_reg_rs2; div.io.dpath_rs2 := ex_reg_rs2;
@ -290,7 +296,8 @@ class rocketDpath extends Component
io.ctrl.div_result_val := div.io.div_result_val; io.ctrl.div_result_val := div.io.div_result_val;
// multiplier // multiplier
mul.io.mul_val := ex_reg_ctrl_mul_val && !io.ctrl.killx; mul.io.mul_val := ex_reg_ctrl_mul_val;
mul.io.mul_kill:= mem_reg_ctrl_mul_val && io.ctrl.killm;
mul.io.dw := ex_reg_ctrl_fn_dw; mul.io.dw := ex_reg_ctrl_fn_dw;
mul.io.mul_fn := ex_reg_ctrl_mul_fn; mul.io.mul_fn := ex_reg_ctrl_mul_fn;
mul.io.mul_tag := ex_reg_waddr; mul.io.mul_tag := ex_reg_waddr;
@ -355,6 +362,8 @@ class rocketDpath extends Component
mem_reg_wdata <== ex_wdata; mem_reg_wdata <== ex_wdata;
mem_reg_ctrl_ll_wb <== ex_reg_ctrl_ll_wb; mem_reg_ctrl_ll_wb <== ex_reg_ctrl_ll_wb;
mem_reg_raddr2 <== ex_reg_raddr2; mem_reg_raddr2 <== ex_reg_raddr2;
mem_reg_ctrl_mul_val <== ex_reg_ctrl_mul_val;
mem_reg_ctrl_div_val <== ex_reg_ctrl_div_val;
when (io.ctrl.killx) { when (io.ctrl.killx) {
mem_reg_valid <== Bool(false); mem_reg_valid <== Bool(false);
@ -378,15 +387,19 @@ class rocketDpath extends Component
r_dmem_resp_replay <== io.dmem.resp_replay; r_dmem_resp_replay <== io.dmem.resp_replay;
r_dmem_resp_waddr <== io.dmem.resp_tag.toUFix r_dmem_resp_waddr <== io.dmem.resp_tag.toUFix
wb_reg_pc <== mem_reg_pc;
wb_reg_waddr <== mem_reg_waddr; wb_reg_waddr <== mem_reg_waddr;
wb_reg_wdata <== mem_reg_wdata; wb_reg_wdata <== mem_reg_wdata;
wb_reg_ctrl_ll_wb <== mem_reg_ctrl_ll_wb; wb_reg_ctrl_ll_wb <== mem_reg_ctrl_ll_wb;
wb_reg_raddr2 <== mem_reg_raddr2;
when (io.ctrl.killm) { when (io.ctrl.killm) {
wb_reg_ctrl_wen <== Bool(false); wb_reg_ctrl_wen <== Bool(false);
wb_reg_ctrl_wen_pcr <== Bool(false);
} }
otherwise { otherwise {
wb_reg_ctrl_wen <== mem_reg_ctrl_wen && !io.dmem.resp_miss; wb_reg_ctrl_wen <== mem_reg_ctrl_wen && !io.dmem.resp_miss;
wb_reg_ctrl_wen_pcr <== mem_reg_ctrl_wen_pcr;
} }
// crossbar/sign extension for 8/16 bit loads (moved to earlier in file) // crossbar/sign extension for 8/16 bit loads (moved to earlier in file)
@ -403,16 +416,16 @@ class rocketDpath extends Component
io.ctrl.sboard_clra := id_waddr; io.ctrl.sboard_clra := id_waddr;
// processor control regfile write // processor control regfile write
pcr.io.w.addr := mem_reg_raddr2; pcr.io.w.addr := wb_reg_raddr2;
pcr.io.w.en := mem_reg_ctrl_wen_pcr && !io.ctrl.killm; pcr.io.w.en := wb_reg_ctrl_wen_pcr;
pcr.io.w.data := mem_reg_wdata; pcr.io.w.data := wb_reg_wdata;
pcr.io.di := io.ctrl.irq_disable; pcr.io.di := io.ctrl.irq_disable;
pcr.io.ei := io.ctrl.irq_enable; pcr.io.ei := io.ctrl.irq_enable;
pcr.io.eret := io.ctrl.mem_eret; pcr.io.eret := io.ctrl.wb_eret;
pcr.io.exception := io.ctrl.exception; pcr.io.exception := io.ctrl.exception;
pcr.io.cause := io.ctrl.cause; pcr.io.cause := io.ctrl.cause;
pcr.io.pc := mem_reg_pc; pcr.io.pc := wb_reg_pc;
pcr.io.badvaddr_wen := io.ctrl.badvaddr_wen; pcr.io.badvaddr_wen := io.ctrl.badvaddr_wen;
io.console.bits := pcr.io.console_data; io.console.bits := pcr.io.console_data;
io.console.valid := pcr.io.console_val; io.console.valid := pcr.io.console_val;

3
rocket/src/main/scala/multiplier.scala
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@ -7,6 +7,7 @@ import Constants._;
class ioMultiplier(width: Int) extends Bundle { class ioMultiplier(width: Int) extends Bundle {
// requests // requests
val mul_val = Bool('input); val mul_val = Bool('input);
val mul_kill= Bool('input);
val mul_rdy = Bool('output); val mul_rdy = Bool('output);
val dw = UFix(1, 'input); val dw = UFix(1, 'input);
val mul_fn = UFix(2, 'input); val mul_fn = UFix(2, 'input);
@ -61,7 +62,7 @@ class rocketMultiplier extends Component {
r_prod<== rhs_in r_prod<== rhs_in
r_lsb <== Bool(false) r_lsb <== Bool(false)
} }
when (io.result_val && io.result_rdy) { when (io.result_val && io.result_rdy || io.mul_kill) {
r_val <== Bool(false) r_val <== Bool(false)
} }