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Merge pull request #753 from freechipsproject/debug_tests

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Debug Tests
This commit is contained in:
Wesley W. Terpstra
2017-05-18 22:20:21 -07:00
committed by GitHub
parent ada5439c3e 24a533e77c
commit 20704b1454
2 changed files with 8 additions and 26 deletions
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32
regression/Makefile
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@@ -216,27 +216,9 @@ stamps/%/emulator-torture-$(TORTURE_CONFIG).stamp: stamps/%/emulator-debug.stamp
# Targets for JTAG DTM full-chain simulation # Targets for JTAG DTM full-chain simulation
#OPENOCD_HEAD ?= riscv OPENOCD_DIR ?= $(RISCV)
OPENOCD_INSTALL ?= $(abspath $(TOP))/riscv-openocd-install
#OPENOCD_VERSION = $(shell git ls-remote git@github.com/riscv/riscv-openocd.git $(OPENOCD_HEAD) | awk '{print $$1}')
OPENOCD_VERSION = 0e66b07550de9076620e45d1f90e38ac6ef8f9d1
OPENOCD_DIR = $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/
$(OPENOCD_DIR)/bin/openocd:
rm -rf riscv-openocd
git clone git@github.com:riscv/riscv-openocd.git
cd riscv-openocd ; \
git checkout $(OPENOCD_VERSION) ; \
./bootstrap ; \
./configure --enable-jtag-vpi --prefix=$(OPENOCD_INSTALL)_$(OPENOCD_VERSION) --disable-werror; \
make ; \
make install
install_openocd: $(OPENOCD_DIR)/bin/openocd
# If this is defined empty, then all tests would run. # If this is defined empty, then all tests would run.
# Running a list of tests is not supported.
JTAG_DTM_TEST ?= MemTest64 JTAG_DTM_TEST ?= MemTest64
ifdef DEBUG ifdef DEBUG
@@ -249,19 +231,19 @@ else
JTAG_STAMP_SUFFIX=-ndebug JTAG_STAMP_SUFFIX=-ndebug
endif endif
stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim$(JTAG_STAMP_SUFFIX).stamp stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFFIX).stamp
export RISCV=$(RISCV) && $(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \ export RISCV=$(RISCV) && $(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
--run "$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(JTAG_VCDPLUS_32)" \ --sim_cmd "$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(JTAG_VCDPLUS_32)" \
--cmd="$(OPENOCD_DIR)/bin/openocd $(OPENOCD_DEBUG) \ --server_cmd="$(OPENOCD_DIR)/bin/openocd $(OPENOCD_DEBUG) \
--s $(OPENOCD_DIR)/share/openocd/scripts" \ --s $(OPENOCD_DIR)/share/openocd/scripts" \
--freedom-e300-sim \ --freedom-e300-sim \
$(JTAG_DTM_TEST) $(JTAG_DTM_TEST)
date > $@ date > $@
stamps/%/jtag-dtm-64-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim$(JTAG_STAMP_SUFFIX).stamp stamps/%/jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFFIX).stamp
export RISCV=$(RISCV) && $(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \ export RISCV=$(RISCV) && $(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
--run "$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(JTAG_VCDPLUS_64)" \ --sim_cmd "$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(JTAG_VCDPLUS_64)" \
--cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd $(OPENOCD_DEBUG) \ --server_cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd $(OPENOCD_DEBUG) \
--s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \ --s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \
--freedom-u500-sim \ --freedom-u500-sim \
$(JTAG_DTM_TEST) $(JTAG_DTM_TEST)

2
riscv-tools

Submodule riscv-tools updated: cf73699997...14bbe5a2e5