riscv/rocket-chip
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Factor coreplex IO connection into separate trait (#350)

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This would allow, for instance, putting the coreplex on a separate clock
domain and crossing the IOs over through asynchronous queues.

The ExampleMultiClockTop* classes are removed since they no longer fit
into the class hierarchy.
This commit is contained in:
Howard Mao 2016-09-27 11:55:32 -07:00 committed by Henry Cook
parent 6316ebd58f
commit 201e247f73
3 changed files with 11 additions and 18 deletions
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2
src/main/scala/coreplex/BaseCoreplex.scala
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@ -59,6 +59,8 @@ abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Paramet
val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput
val resetVector = UInt(INPUT, p(XLen)) val resetVector = UInt(INPUT, p(XLen))
val success = Bool(OUTPUT) // used for testing val success = Bool(OUTPUT) // used for testing
override def cloneType = this.getClass.getConstructors.head.newInstance(c, p).asInstanceOf[this.type]
} }
abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle]( abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](

9
src/main/scala/rocketchip/BaseTop.scala
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@ -67,7 +67,7 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](
val io: B = b val io: B = b
val coreplex = p(BuildCoreplex)(outer.c, p) val coreplex = p(BuildCoreplex)(outer.c, p)
val coreplexIO = coreplex.io val coreplexIO = Wire(coreplex.io)
val pBus = val pBus =
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:pbus"))( Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:pbus"))(
@ -95,3 +95,10 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](
io.success := coreplexIO.success io.success := coreplexIO.success
} }
trait DirectConnection {
val coreplexIO: BaseCoreplexBundle
val coreplex: BaseCoreplexModule[BaseCoreplex, BaseCoreplexBundle]
coreplexIO <> coreplex.io
}

18
src/main/scala/rocketchip/ExampleTop.scala
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@ -38,6 +38,7 @@ class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters,
with PeripheryMasterMMIOModule with PeripheryMasterMMIOModule
with PeripherySlaveModule with PeripherySlaveModule
with HardwiredResetVector with HardwiredResetVector
with DirectConnection
/** Example Top with TestRAM */ /** Example Top with TestRAM */
class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q) class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
@ -50,20 +51,3 @@ class ExampleTopWithTestRAMBundle(p: Parameters) extends ExampleTopBundle(p)
class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: => B) extends ExampleTopModule(p, l, b) class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: => B) extends ExampleTopModule(p, l, b)
with PeripheryTestRAMModule with PeripheryTestRAMModule
/** Example Top with Multi Clock */
class ExampleMultiClockTop(q: Parameters) extends ExampleTop(q)
with PeripheryTestRAM {
override lazy val module = Module(new ExampleMultiClockTopModule(p, this, new ExampleMultiClockTopBundle(p)))
}
class ExampleMultiClockTopBundle(p: Parameters) extends ExampleTopBundle(p)
class ExampleMultiClockTopModule[+L <: ExampleMultiClockTop, +B <: ExampleMultiClockTopBundle](p: Parameters, l: L, b: => B) extends ExampleTopModule(p, l, b) {
val multiClockCoreplexIO = coreplexIO.asInstanceOf[MultiClockCoreplexBundle]
multiClockCoreplexIO.tcrs foreach { tcr =>
tcr.clock := clock
tcr.reset := reset
}
}