riscv/rocket-chip
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Support superpage entries in TLB

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This commit is contained in:
Andrew Waterman
2017-03-12 20:42:51 -07:00
parent 2d267b4940
commit 1fea0460ba
5 changed files with 74 additions and 61 deletions
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4
src/main/scala/rocket/NBDcache.scala
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@ -700,7 +700,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
io.ptw <> dtlb.io.ptw
dtlb.io.req.valid := s1_valid_masked && s1_readwrite
dtlb.io.req.bits.passthrough := s1_req.phys
dtlb.io.req.bits.vpn := s1_req.addr >> pgIdxBits
dtlb.io.req.bits.vaddr := s1_req.addr
dtlb.io.req.bits.instruction := Bool(false)
dtlb.io.req.bits.store := s1_write
when (!dtlb.io.req.ready && !io.cpu.req.bits.phys) { io.cpu.req.ready := Bool(false) }
@ -722,7 +722,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
when (s2_recycle) {
s1_req := s2_req
}
val s1_addr = Cat(dtlb.io.resp.ppn, s1_req.addr(pgIdxBits-1,0))
val s1_addr = dtlb.io.resp.paddr
when (s1_clk_en) {
s2_req.typ := s1_req.typ