riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Support superpage entries in TLB

Browse Source
This commit is contained in:
Andrew Waterman
2017-03-12 20:42:51 -07:00
parent 2d267b4940
commit 1fea0460ba
5 changed files with 74 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/rocket/Frontend.scala
View File

@ -129,7 +129,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
io.ptw <> tlb.io.ptw
tlb.io.req.valid := !stall && !icmiss
tlb.io.req.bits.vpn := s1_pc >> pgIdxBits
tlb.io.req.bits.vaddr := s1_pc
tlb.io.req.bits.passthrough := Bool(false)
tlb.io.req.bits.instruction := Bool(true)
tlb.io.req.bits.store := Bool(false)
@ -137,7 +137,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
icache.io.req.valid := !stall && !s0_same_block
icache.io.req.bits.addr := io.cpu.npc
icache.io.invalidate := io.cpu.flush_icache
icache.io.s1_paddr := Cat(tlb.io.resp.ppn, s1_pc(pgIdxBits-1, 0))
icache.io.s1_paddr := tlb.io.resp.paddr
icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || tlb.io.resp.xcpt_if || icmiss || io.cpu.flush_tlb
icache.io.s2_kill := s2_speculative && !s2_cacheable
icache.io.resp.ready := !stall && !s1_same_block