riscv/rocket-chip
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Support superpage entries in TLB

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This commit is contained in:
Andrew Waterman
2017-03-12 20:42:51 -07:00
parent 2d267b4940
commit 1fea0460ba
5 changed files with 74 additions and 61 deletions
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4
src/main/scala/rocket/DCache.scala
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@ -105,13 +105,13 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
io.ptw <> tlb.io.ptw
tlb.io.req.valid := s1_valid_masked && s1_readwrite
tlb.io.req.bits.passthrough := s1_req.phys
tlb.io.req.bits.vpn := s1_req.addr >> pgIdxBits
tlb.io.req.bits.vaddr := s1_req.addr
tlb.io.req.bits.instruction := false
tlb.io.req.bits.store := s1_write
when (!tlb.io.req.ready && !io.cpu.req.bits.phys) { io.cpu.req.ready := false }
when (s1_valid && s1_readwrite && tlb.io.resp.miss) { s1_nack := true }
val s1_paddr = Cat(tlb.io.resp.ppn, s1_req.addr(pgIdxBits-1,0))
val s1_paddr = tlb.io.resp.paddr
val s1_tag = Mux(s1_probe, probe_bits.address, s1_paddr)(paddrBits-1, untagBits)
val s1_victim_way = Wire(init = replacer.way)
val (s1_hit_way, s1_hit_state, s1_victim_meta) =