From 1fa505f9ff44cd49fc90866640d37f74b0b1200b Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 16 Apr 2014 17:19:08 -0700 Subject: [PATCH] remove superfluous AVec object --- rocket/src/main/scala/ctrl.scala | 2 +- rocket/src/main/scala/nbdcache.scala | 12 ++++++------ rocket/src/main/scala/ptw.scala | 4 ++-- rocket/src/main/scala/util.scala | 12 ------------ 4 files changed, 9 insertions(+), 21 deletions(-) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 8317777f..6148fcf4 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -512,7 +512,7 @@ class Control(implicit conf: RocketConfiguration) extends Module val replay_ex = replay_ex_structural || replay_ex_other ctrl_killx := take_pc_mem_wb || replay_ex // detect 2-cycle load-use delay for LB/LH/SC - val ex_slow_bypass = ex_reg_mem_cmd === M_XSC || AVec(MT_B, MT_BU, MT_H, MT_HU).contains(ex_reg_mem_type) + val ex_slow_bypass = ex_reg_mem_cmd === M_XSC || Vec(MT_B, MT_BU, MT_H, MT_HU).contains(ex_reg_mem_type) val (ex_xcpt, ex_cause) = checkExceptions(List( (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause), diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index a4b686e5..974646cb 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -637,10 +637,10 @@ class DataArray(implicit conf: DCacheConfig) extends Module { resp(p) := array(RegEnable(raddr, rway_en.orR && io.read.valid)) } for (dw <- 0 until conf.rowwords) { - val r = AVec(resp.map(_(conf.encdatabits*(dw+1)-1,conf.encdatabits*dw))) + val r = Vec(resp.map(_(conf.encdatabits*(dw+1)-1,conf.encdatabits*dw))) val resp_mux = if (r.size == 1) r - else AVec(r(r_raddr(conf.rowoffbits-1,conf.wordoffbits)), r.tail:_*) + else Vec(r(r_raddr(conf.rowoffbits-1,conf.wordoffbits)), r.tail:_*) io.resp(w+dw) := resp_mux.toBits } } @@ -849,7 +849,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module { writeArb.io.out.ready := data.io.write.ready data.io.write.bits := writeArb.io.out.bits val wdata_encoded = (0 until conf.rowwords).map(i => conf.code.encode(writeArb.io.out.bits.data(conf.databits*(i+1)-1,conf.databits*i))) - data.io.write.bits.data := AVec(wdata_encoded).toBits + data.io.write.bits.data := Vec(wdata_encoded).toBits // tag read for new requests metaReadArb.io.in(4).valid := io.cpu.req.valid @@ -911,10 +911,10 @@ class HellaCache(implicit conf: DCacheConfig) extends Module { } val s2_data_muxed = Mux1H(s2_tag_match_way, s2_data) val s2_data_decoded = (0 until conf.rowwords).map(i => conf.code.decode(s2_data_muxed(conf.encdatabits*(i+1)-1,conf.encdatabits*i))) - val s2_data_corrected = AVec(s2_data_decoded.map(_.corrected)).toBits - val s2_data_uncorrected = AVec(s2_data_decoded.map(_.uncorrected)).toBits + val s2_data_corrected = Vec(s2_data_decoded.map(_.corrected)).toBits + val s2_data_uncorrected = Vec(s2_data_decoded.map(_.uncorrected)).toBits val s2_word_idx = if (conf.isNarrowRead) UInt(0) else s2_req.addr(log2Up(conf.rowwords*conf.databytes)-1,3) - val s2_data_correctable = AVec(s2_data_decoded.map(_.correctable)).toBits()(s2_word_idx) + val s2_data_correctable = Vec(s2_data_decoded.map(_.correctable)).toBits()(s2_word_idx) // store/amo hits s3_valid := (s2_valid_masked && s2_hit || s2_replay) && !s2_sc_fail && isWrite(s2_req.cmd) diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala index 22b86da2..f72e0b14 100644 --- a/rocket/src/main/scala/ptw.scala +++ b/rocket/src/main/scala/ptw.scala @@ -48,7 +48,7 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module val r_req_dest = Reg(Bits()) val r_pte = Reg(Bits()) - val vpn_idx = AVec((0 until levels).map(i => (r_req_vpn >> (levels-i-1)*bitsPerLevel)(bitsPerLevel-1,0)))(count) + val vpn_idx = Vec((0 until levels).map(i => (r_req_vpn >> (levels-i-1)*bitsPerLevel)(bitsPerLevel-1,0)))(count) val arb = Module(new RRArbiter(UInt(width = conf.as.vpnBits), n)) arb.io.in <> io.requestor.map(_.req) @@ -75,7 +75,7 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module val resp_err = state === s_error || state === s_wait val r_resp_ppn = io.mem.req.bits.addr >> conf.as.pgIdxBits - val resp_ppn = AVec((0 until levels-1).map(i => Cat(r_resp_ppn >> bitsPerLevel*(levels-i-1), r_req_vpn(bitsPerLevel*(levels-i-1)-1,0))) :+ r_resp_ppn)(count) + val resp_ppn = Vec((0 until levels-1).map(i => Cat(r_resp_ppn >> bitsPerLevel*(levels-i-1), r_req_vpn(bitsPerLevel*(levels-i-1)-1,0))) :+ r_resp_ppn)(count) for (i <- 0 until io.requestor.size) { val me = r_req_dest === UInt(i) diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index 7595ce8b..4a0ef27d 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -21,18 +21,6 @@ object Util { import Util._ -object AVec -{ - def apply[T <: Data](elts: Seq[T]): Vec[T] = Vec(elts) - def apply[T <: Data](elts: Vec[T]): Vec[T] = apply(elts.toSeq) - def apply[T <: Data](elt0: T, elts: T*): Vec[T] = apply(elt0 :: elts.toList) - - def tabulate[T <: Data](n: Int)(f: Int => T): Vec[T] = - apply((0 until n).map(i => f(i))) - def tabulate[T <: Data](n1: Int, n2: Int)(f: (Int, Int) => T): Vec[Vec[T]] = - tabulate(n1)(i1 => tabulate(n2)(f(i1, _))) -} - object Str { def apply(s: String): UInt = {