riscv/rocket-chip
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[rocket] dcache probe ack data bugfix

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This commit is contained in:
Henry Cook
2016-11-16 14:25:21 -08:00
parent 66a2c5544e
commit 1f51564577
2 changed files with 6 additions and 7 deletions
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9
src/main/scala/rocket/dcache.scala
View File

@@ -201,9 +201,8 @@ class DCache(maxUncachedInFlight: Int = 2)(implicit val p: Parameters) extends L
val s2_victim_tag = RegEnable(s1_victim_meta.tag, s1_valid_not_nacked || s1_flush_valid) val s2_victim_tag = RegEnable(s1_victim_meta.tag, s1_valid_not_nacked || s1_flush_valid)
val s2_victim_state = Mux(s2_hit_valid && !s2_flush_valid, s2_hit_state, RegEnable(s1_victim_meta.coh, s1_valid_not_nacked || s1_flush_valid)) val s2_victim_state = Mux(s2_hit_valid && !s2_flush_valid, s2_hit_state, RegEnable(s1_victim_meta.coh, s1_valid_not_nacked || s1_flush_valid))
val s2_victim_valid = s2_victim_state.isValid() val s2_victim_valid = s2_victim_state.isValid()
val (prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param) val (s2_prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param)
val (needs_vol_wb, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH) val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH)
val s2_victim_dirty = needs_vol_wb
val s2_update_meta = s2_hit_state =/= s2_new_hit_state val s2_update_meta = s2_hit_state =/= s2_new_hit_state
io.cpu.s2_nack := s2_valid && !s2_valid_hit && !(s2_valid_uncached && tl_out.a.ready && !uncachedInFlight.asUInt.andR) io.cpu.s2_nack := s2_valid && !s2_valid_hit && !(s2_valid_uncached && tl_out.a.ready && !uncachedInFlight.asUInt.andR)
when (s2_valid && (!s2_valid_hit || s2_update_meta)) { s1_nack := true } when (s2_valid && (!s2_valid_hit || s2_update_meta)) { s1_nack := true }
@@ -408,7 +407,7 @@ class DCache(maxUncachedInFlight: Int = 2)(implicit val p: Parameters) extends L
shrinkPermissions = s2_shrink_param, shrinkPermissions = s2_shrink_param,
data = s2_data)._2 data = s2_data)._2
val probeResponseMessage = Mux(prb_ack_data, val probeResponseMessage = Mux(s2_prb_ack_data,
edge.ProbeAck( edge.ProbeAck(
b = probe_bits, b = probe_bits,
reportPermissions = s2_report_param), reportPermissions = s2_report_param),
@@ -428,7 +427,7 @@ class DCache(maxUncachedInFlight: Int = 2)(implicit val p: Parameters) extends L
probe_bits.address := Cat(s2_victim_tag, s2_req.addr(idxMSB, idxLSB)) << idxLSB probe_bits.address := Cat(s2_victim_tag, s2_req.addr(idxMSB, idxLSB)) << idxLSB
} }
when (s2_probe) { when (s2_probe) {
when (needs_vol_wb) { release_state := s_probe_rep_dirty } when (s2_prb_ack_data) { release_state := s_probe_rep_dirty }
.elsewhen (s2_probe_state.isValid()) { release_state := s_probe_rep_clean } .elsewhen (s2_probe_state.isValid()) { release_state := s_probe_rep_clean }
.otherwise { .otherwise {
tl_out.c.valid := true tl_out.c.valid := true

4
src/main/scala/uncore/tilelink2/Metadata.scala
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@@ -107,7 +107,7 @@ class ClientMetadata extends Bundle {
import ClientStates._ import ClientStates._
import TLPermissions._ import TLPermissions._
MuxTLookup(Cat(param, state), (Bool(false), UInt(0), UInt(0)), Seq( MuxTLookup(Cat(param, state), (Bool(false), UInt(0), UInt(0)), Seq(
//(wanted, am now) -> (dirtyWB resp, next) //(wanted, am now) -> (hasDirtyData resp, next)
Cat(toT, Dirty) -> (Bool(true), TtoT, Trunk), Cat(toT, Dirty) -> (Bool(true), TtoT, Trunk),
Cat(toT, Trunk) -> (Bool(false), TtoT, Trunk), Cat(toT, Trunk) -> (Bool(false), TtoT, Trunk),
Cat(toT, Branch) -> (Bool(false), BtoB, Branch), Cat(toT, Branch) -> (Bool(false), BtoB, Branch),
@@ -139,7 +139,7 @@ class ClientMetadata extends Bundle {
def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = {
val r = shrinkHelper(param) val r = shrinkHelper(param)
(Bool(true), r._2, ClientMetadata(r._3)) (r._1, r._2, ClientMetadata(r._3))
} }
} }