diplomacy: appease Jack by removing unused 1st bundles argument
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@ -18,8 +18,8 @@ trait InwardNodeImp[DI, UI, EI, BI <: Data]
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def bundleI(ei: EI): BI
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def bundleI(ei: EI): BI
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def colour: String
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def colour: String
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def reverse: Boolean = false
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def reverse: Boolean = false
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def connect(edges: () => Seq[EI], bundles: () => Seq[(EI, BI, BI)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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def connect(edges: () => Seq[EI], bundles: () => Seq[(BI, BI)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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(None, () => bundles().foreach { case (_, i, o) => i <> o })
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(None, () => bundles().foreach { case (i, o) => i <> o })
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}
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}
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// optional methods to track node graph
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// optional methods to track node graph
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@ -255,7 +255,7 @@ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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val (oStart, oEnd) = y.oPortMapping(o)
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val (oStart, oEnd) = y.oPortMapping(o)
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require (iEnd - iStart == oEnd - oStart, s"Bug in diplomacy; ${iEnd-iStart} != ${oEnd-oStart} means port resolution failed")
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require (iEnd - iStart == oEnd - oStart, s"Bug in diplomacy; ${iEnd-iStart} != ${oEnd-oStart} means port resolution failed")
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Seq.tabulate(iEnd - iStart) { j =>
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Seq.tabulate(iEnd - iStart) { j =>
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(x.edgesIn(iStart+j), x.bundleIn(iStart+j), y.bundleOut(oStart+j))
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(x.bundleIn(iStart+j), y.bundleOut(oStart+j))
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}
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}
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}
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}
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val (out, newbinding) = inner.connect(edges _, bundles _)
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val (out, newbinding) = inner.connect(edges _, bundles _)
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@ -25,12 +25,12 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
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override def labelI(ei: TLEdgeIn) = (ei.manager.beatBytes * 8).toString
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override def labelI(ei: TLEdgeIn) = (ei.manager.beatBytes * 8).toString
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override def labelO(eo: TLEdgeOut) = (eo.manager.beatBytes * 8).toString
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override def labelO(eo: TLEdgeOut) = (eo.manager.beatBytes * 8).toString
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override def connect(edges: () => Seq[TLEdgeIn], bundles: () => Seq[(TLEdgeIn, TLBundle, TLBundle)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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override def connect(edges: () => Seq[TLEdgeIn], bundles: () => Seq[(TLBundle, TLBundle)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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val monitor = p(TLMonitorBuilder)(TLMonitorArgs(edges, sourceInfo, p))
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val monitor = p(TLMonitorBuilder)(TLMonitorArgs(edges, sourceInfo, p))
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(monitor, () => {
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(monitor, () => {
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val eval = bundles ()
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val eval = bundles ()
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monitor.foreach { m => (eval zip m.module.io.in) foreach { case ((_,i,o), m) => m := TLBundleSnoop(o,i) } }
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monitor.foreach { m => (eval zip m.module.io.in) foreach { case ((i,o), m) => m := TLBundleSnoop(o,i) } }
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eval.foreach { case (_, bi, bo) =>
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eval.foreach { case (bi, bo) =>
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bi <> bo
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bi <> bo
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if (p(TLCombinationalCheck)) {
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if (p(TLCombinationalCheck)) {
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// It is forbidden for valid to depend on ready in TL2
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// It is forbidden for valid to depend on ready in TL2
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