riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

WIP on new memory map

Browse Source
This commit is contained in:
Andrew Waterman
2016-04-27 14:57:54 -07:00
parent 48170fd9aa
commit 1f211b37df
17 changed files with 110 additions and 466 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
vsim/Makefrag-verilog
View File

@ -10,9 +10,6 @@ $(generated_dir)/$(MODEL).$(CONFIG).v $(generated_dir)/$(MODEL).$(CONFIG).d $(ge
$(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $(generated_dir)/$(MODEL).$(CONFIG).v; \
fi
$(generated_dir)/memdessertMemDessert.$(CONFIG).v $(generated_dir)/memdessertMemDessert.$(CONFIG).d: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(PROJECT) MemDessert $(CONFIG) --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configName $(CONFIG)"
else
FIRRTL ?= $(base_dir)/firrtl/utils/bin/firrtl
@ -23,7 +20,6 @@ $(FIRRTL):
# If I don't mark these as .SECONDARY then make will delete these internal
# files.
.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
.SECONDARY: $(generated_dir)/MemDessert.$(CONFIG).fir
$(generated_dir)/%.$(CONFIG).fir: $(chisel_srcs)
mkdir -p $(dir $@)
@ -34,12 +30,6 @@ $(generated_dir)/%.v $(generated_dir)/%.prm: $(generated_dir)/%.fir $(FIRRTL)
mkdir -p $(dir $@)
$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog
$(generated_dir)/memdessertMemDessert.$(CONFIG).v: $(generated_dir)/MemDessert.$(CONFIG).v
cat $(filter %.v,$^) \
| sed 's@MemDessert@memdessertMemDessert@g' \
| sed 's@Queue@memdessetQueue@g' \
> $@
endif
$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).prm