WIP on new memory map
This commit is contained in:
Andrew Waterman
@ -25,24 +25,23 @@ class DefaultConfig extends Config (
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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def genCsrAddrMap: AddrMap = {
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val deviceTree = AddrMapEntry("devicetree", None, MemSize(1 << 15, AddrMapConsts.R))
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val csrSize = (1 << 12) * (site(XLen) / 8)
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val csrs = (0 until site(NTiles)).map{ i =>
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AddrMapEntry(s"csr$i", None, MemSize(csrSize, AddrMapConsts.RW))
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}
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val scrSize = site(HtifKey).nSCR * (site(XLen) / 8)
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val scr = AddrMapEntry("scr", None, MemSize(scrSize, AddrMapConsts.RW))
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new AddrMap(deviceTree +: csrs :+ scr)
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val deviceTree = AddrMapEntry("devicetree", MemSize(1 << 15, AddrMapConsts.R))
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val rtc = AddrMapEntry("rtc", MemSize(1 << 12, AddrMapConsts.RW))
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new AddrMap(Seq(deviceTree, rtc))
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}
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def makeConfigString() = {
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val addrMap = new AddrHashMap(site(GlobalAddrMap))
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val xLen = site(XLen)
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val res = new StringBuilder
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val memSize = addrMap(s"mem").size
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val memSize = addrMap("mem").size
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val rtcAddr = addrMap("conf:rtc").start
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res append "platform {\n"
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res append " vendor ucb;\n"
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res append " arch rocket;\n"
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res append "};\n"
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res append "rtc {\n"
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res append s" addr 0x${rtcAddr.toString(16)};\n"
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res append "};\n"
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res append "ram {\n"
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res append " 0 {\n"
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res append " addr 0;\n"
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@ -51,11 +50,11 @@ class DefaultConfig extends Config (
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res append "};\n"
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res append "core {\n"
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for (i <- 0 until site(NTiles)) {
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val csrAddr = addrMap(s"conf:csr$i").start
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val timecmpAddr = rtcAddr + 8*(i+1)
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res append s" $i {\n"
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res append " 0 {\n"
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res append s" isa rv$xLen;\n"
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res append s" addr 0x${csrAddr.toString(16)};\n"
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res append s" timecmp 0x${timecmpAddr.toString(16)};\n"
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res append " };\n"
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res append " };\n"
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}
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@ -187,7 +186,7 @@ class DefaultConfig extends Config (
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case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
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case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
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log2Up(site(TLKey(site(TLId))).nClients)
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case ExtraL1Clients => 2 // RTC and HTIF
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case ExtraL1Clients => 1 // HTIF // TODO not really a parameter
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case TLKey("L1toL2") =>
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TileLinkParameters(
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coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
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@ -201,9 +200,7 @@ class DefaultConfig extends Config (
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// L1 cache
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site(NMSHRs) + 1,
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// RoCC
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts),
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// RTC
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site(NTiles)),
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
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maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBits = site(CacheBlockBytes)*8)
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@ -245,18 +242,15 @@ class DefaultConfig extends Config (
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case BankIdLSB => 0
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case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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case UseBackupMemoryPort => false
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case UseHtifClockDiv => true
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case ConfigString => makeConfigString()
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case GlobalAddrMap => {
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val memsize = BigInt(1L << 30)
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Dump("MEM_SIZE", memsize)
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AddrMap(
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AddrMapEntry("mem", None, MemSize(memsize, AddrMapConsts.RWX, true)),
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AddrMapEntry("conf", None,
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MemSubmap(BigInt(1L << 30), genCsrAddrMap)),
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AddrMapEntry("devices", None,
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MemSubmap(BigInt(1L << 31), site(GlobalDeviceSet).getAddrMap)))
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AddrMapEntry("mem", MemSize(memsize, AddrMapConsts.RWX, true)),
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AddrMapEntry("conf", MemSubmap(BigInt(1L << 30), genCsrAddrMap)),
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AddrMapEntry("devices", MemSubmap(BigInt(1L << 31), site(GlobalDeviceSet).getAddrMap)))
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}
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case GlobalDeviceSet => {
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val devset = new DeviceSet
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@ -29,7 +29,7 @@ class DeviceSet {
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val entries = devices.map { case Device(name, size, _, readable, writeable) =>
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val prot = (if (readable) R else 0) | (if (writeable) W else 0)
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val realsize = roundup(size)
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new AddrMapEntry(name, None, new MemSize(realsize, prot))
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new AddrMapEntry(name, new MemSize(realsize, prot))
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}
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new AddrMap(entries)
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}
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@ -25,8 +25,6 @@ case object MemoryChannelMuxConfigs extends Field[List[Int]]
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case object BankIdLSB extends Field[Int]
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/** Number of outstanding memory requests */
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case object NOutstandingMemReqsPerChannel extends Field[Int]
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/** Whether to use the slow backup memory port [VLSI] */
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case object UseBackupMemoryPort extends Field[Boolean]
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/** Whether to divide HTIF clock */
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case object UseHtifClockDiv extends Field[Boolean]
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/** Function for building some kind of coherence manager agent */
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@ -78,7 +76,6 @@ class MemBackupCtrlIO extends Bundle {
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class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasTopLevelParameters {
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val host = new HostIO(htifW)
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val mem_backup_ctrl = new MemBackupCtrlIO
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}
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class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
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@ -95,6 +92,11 @@ object TopUtils {
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inner.r <> Queue(outer.r, mifDataBeats)
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inner.b <> Queue(outer.b)
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}
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def connectTilelinkNasti(nasti: NastiIO, tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val conv = Module(new NastiIOTileLinkIOConverter())
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conv.io.tl <> tl
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TopUtils.connectNasti(nasti, conv.io.nasti)
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}
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}
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/** Top-level module for the chip */
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@ -111,19 +113,17 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
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// Connect each tile to the HTIF
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uncore.io.htif.zip(tileList).zipWithIndex.foreach {
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case ((hl, tile), i) =>
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tile.io.host.timerIRQ := uncore.io.timerIRQs(i)
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tile.io.host.id := UInt(i)
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tile.io.host.reset := Reg(next=Reg(next=hl.reset))
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tile.io.host.csr.req <> Queue(hl.csr.req)
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hl.csr.resp <> Queue(tile.io.host.csr.resp)
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hl.debug_stats_csr := tile.io.host.debug_stats_csr
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}
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// Connect the uncore to the tile memory ports, HostIO and MemIO
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uncore.io.tiles_cached <> tileList.map(_.io.cached).flatten
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uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
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io.host <> uncore.io.host
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if (p(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
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else { uncore.io.mem_backup_ctrl.en := Bool(false) }
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io.mem.zip(uncore.io.mem).foreach { case (outer, inner) =>
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TopUtils.connectNasti(outer, inner)
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@ -146,7 +146,7 @@ class Uncore(implicit val p: Parameters) extends Module
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val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
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val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
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val htif = Vec(nTiles, new HtifIO).flip
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val mem_backup_ctrl = new MemBackupCtrlIO
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val timerIRQs = Vec(nTiles, Bool()).asOutput
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val mmio = new NastiIO
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}
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@ -160,25 +160,20 @@ class Uncore(implicit val p: Parameters) extends Module
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for (i <- 0 until nTiles) {
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io.htif(i).reset := htif.io.cpu(i).reset
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io.htif(i).id := htif.io.cpu(i).id
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htif.io.cpu(i).debug_stats_csr <> io.htif(i).debug_stats_csr
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val csr_arb = Module(new SmiArbiter(2, xLen, csrAddrBits))
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csr_arb.io.in(0) <> htif.io.cpu(i).csr
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csr_arb.io.in(1) <> outmemsys.io.csr(i)
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io.htif(i).csr <> csr_arb.io.out
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io.htif(i).csr <> htif.io.cpu(i).csr
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}
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// Arbitrate SCR access between MMIO and HTIF
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val addrHashMap = new AddrHashMap(p(GlobalAddrMap))
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val scrFile = Module(new SCRFile("UNCORE_SCR",addrHashMap("conf:scr").start))
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val scrArb = Module(new SmiArbiter(2, scrDataBits, scrAddrBits))
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scrArb.io.in(0) <> htif.io.scr
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scrArb.io.in(1) <> outmemsys.io.scr
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scrFile.io.smi <> scrArb.io.out
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val addrMap = p(GlobalAddrMap)
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val addrHashMap = new AddrHashMap(addrMap)
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val memSize = addrHashMap("mem").size
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val scrFile = Module(new SCRFile("UNCORE_SCR", 0))
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scrFile.io.smi <> htif.io.scr
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scrFile.io.scr.attach(Wire(init = UInt(nTiles)), "N_CORES")
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scrFile.io.scr.attach(Wire(init = UInt(addrHashMap("mem").size >> 20)), "MMIO_BASE")
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scrFile.io.scr.attach(Wire(init = UInt(memSize >> 20)), "MMIO_BASE")
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// scrFile.io.scr <> (... your SCR connections ...)
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buildMMIONetwork(p.alterPartial({case TLId => "MMIO_Outermost"}))
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// Configures the enabled memory channels. This can't be changed while the
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// chip is actively using memory, as it both drops Nasti messages and garbles
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// all of memory.
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@ -187,19 +182,40 @@ class Uncore(implicit val p: Parameters) extends Module
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"MEMORY_CHANNEL_MUX_SELECT")
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outmemsys.io.memory_channel_mux_select := memory_channel_mux_select
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val deviceTree = Module(new NastiROM(p(ConfigString).toSeq))
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deviceTree.io <> outmemsys.io.deviceTree
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// Wire the htif to the memory port(s) and host interface
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io.host.debug_stats_csr := htif.io.host.debug_stats_csr
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io.mem <> outmemsys.io.mem
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if(p(UseHtifClockDiv)) {
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outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en
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VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr,
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outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW)
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VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr, io.host, htifW)
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} else {
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io.host.out <> htif.io.host.out
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htif.io.host.in <> io.host.in
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io.host <> htif.io.host
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}
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def buildMMIONetwork(implicit p: Parameters) = {
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val mmioNarrower = Module(new TileLinkIONarrower("L2toMMIO", "MMIO_Outermost"))
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val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, addrMap.tail, memSize))
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mmioNarrower.io.in <> outmemsys.io.mmio
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mmioNetwork.io.in.head <> mmioNarrower.io.out
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if (p(UseStreamLoopback)) {
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val lo_width = p(StreamLoopbackWidth)
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val lo_size = p(StreamLoopbackSize)
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val lo_conv = Module(new NastiIOStreamIOConverter(lo_width))
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val lo_port = addrHashMap("devices:loopback").port - 1
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TopUtils.connectTilelinkNasti(lo_conv.io.nasti, mmioNetwork.io.out(lo_port))
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lo_conv.io.stream.in <> Queue(lo_conv.io.stream.out, lo_size)
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}
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val rtc = Module(new RTC(p(NTiles)))
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val rtcAddr = addrHashMap("conf:rtc")
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val rtcPort = rtcAddr.port - 1
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require(rtc.size <= rtcAddr.size)
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rtc.io.tl <> mmioNetwork.io.out(rtcPort)
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io.timerIRQs := rtc.io.irqs
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val deviceTree = Module(new ROMSlave(p(ConfigString).toSeq))
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val dtPort = addrHashMap("conf:devicetree").port - 1
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deviceTree.io <> mmioNetwork.io.out(dtPort)
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}
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}
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@ -213,25 +229,18 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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val htif_uncached = (new ClientUncachedTileLinkIO).flip
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val incoherent = Vec(nTiles, Bool()).asInput
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val mem = Vec(nMemChannels, new NastiIO)
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val mem_backup = new MemSerializedIO(htifW)
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val mem_backup_en = Bool(INPUT)
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val memory_channel_mux_select = UInt(INPUT, log2Up(memoryChannelMuxConfigs.size))
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val csr = Vec(nTiles, new SmiIO(xLen, csrAddrBits))
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val scr = new SmiIO(xLen, scrAddrBits)
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val deviceTree = new NastiIO
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val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"}))
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}
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val addrMap = p(GlobalAddrMap)
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val addrHashMap = new AddrHashMap(addrMap)
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val memSize = addrHashMap("mem").size
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val addrHashMap = new AddrHashMap(p(GlobalAddrMap))
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// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: Bits): UInt = {
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val isMemory = addrHashMap.isInRegion("mem",
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addr.toUInt << log2Up(p(CacheBlockBytes)))
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def addrToBank(addr: UInt): UInt = {
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val isMemory = addrHashMap.isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
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Mux(isMemory,
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if (nBanks > 1) addr(lsb + log2Up(nBanks) - 1, lsb) else UInt(0),
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UInt(nBanks))
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@ -248,13 +257,12 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMMIO"
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})))
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val rtc = Module(new RTC(CSRs.mtime))
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io.mmio <> mmioManager.io.outer
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// Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
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// and coherence manager(s) to the other side
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l1tol2net.io.clients_cached <> io.tiles_cached
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l1tol2net.io.clients_uncached <> io.tiles_uncached ++ Seq(rtc.io, io.htif_uncached)
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l1tol2net.io.clients_uncached <> io.tiles_uncached ++ Seq(io.htif_uncached)
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
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// Create a converter between TileLinkIO and MemIO for each channel
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@ -262,7 +270,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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val outermostTLParams = p.alterPartial({case TLId => "Outermost"})
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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// TODO: the code to print this stuff should live somewhere else
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println("Generated Address Map")
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for ((name, base, size, _, _) <- addrHashMap.sortedEntries) {
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@ -295,67 +302,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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mem_ic.io.in(i) <> narrow.io.out
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}
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val mmioOutermostTLParams = p.alterPartial({case TLId => "MMIO_Outermost"})
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val mmio_narrow = Module(new TileLinkIONarrower("L2toMMIO", "MMIO_Outermost"))
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val mmio_net = Module(new TileLinkRecursiveInterconnect(
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1, addrHashMap.nEntries - 1, addrMap.tail, memSize)(mmioOutermostTLParams))
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//val mmio_conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams))
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mmio_narrow.io.in <> mmioManager.io.outer
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mmio_net.io.in.head <> mmio_narrow.io.out
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def connectTilelinkNasti(nasti: NastiIO, tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val conv = Module(new NastiIOTileLinkIOConverter())
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conv.io.tl <> tl
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TopUtils.connectNasti(nasti, conv.io.nasti)
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}
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for (i <- 0 until nTiles) {
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val csrName = s"conf:csr$i"
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val csrPort = addrHashMap(csrName).port - 1
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val conv = Module(new SmiIONastiIOConverter(xLen, csrAddrBits))
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connectTilelinkNasti(conv.io.nasti, mmio_net.io.out(csrPort))(mmioOutermostTLParams)
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io.csr(i) <> conv.io.smi
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}
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val scrPort = addrHashMap("conf:scr").port - 1
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val scr_conv = Module(new SmiIONastiIOConverter(scrDataBits, scrAddrBits))
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connectTilelinkNasti(scr_conv.io.nasti, mmio_net.io.out(scrPort))(mmioOutermostTLParams)
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io.scr <> scr_conv.io.smi
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if (p(UseStreamLoopback)) {
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val lo_width = p(StreamLoopbackWidth)
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val lo_size = p(StreamLoopbackSize)
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val lo_conv = Module(new NastiIOStreamIOConverter(lo_width))
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val lo_port = addrHashMap("devices:loopback").port - 1
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connectTilelinkNasti(lo_conv.io.nasti, mmio_net.io.out(lo_port))(mmioOutermostTLParams)
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lo_conv.io.stream.in <> Queue(lo_conv.io.stream.out, lo_size)
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}
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val dtPort = addrHashMap("conf:devicetree").port - 1
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connectTilelinkNasti(io.deviceTree, mmio_net.io.out(dtPort))(mmioOutermostTLParams)
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val mem_channels = Wire(Vec(nMemChannels, new NastiIO))
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mem_channels.zip(mem_ic.io.out).foreach { case (ch, out) =>
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connectTilelinkNasti(ch, out)(outermostTLParams)
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}
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// Create a SerDes for backup memory port
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if(p(UseBackupMemoryPort)) {
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VLSIUtils.doOuterMemorySystemSerdes(
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mem_channels, io.mem, io.mem_backup, io.mem_backup_en,
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1, htifW, p(CacheBlockOffsetBits))
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for (i <- 1 until nMemChannels) { io.mem(i) <> mem_channels(i) }
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val mem_request = mem_channels.map(io => io.ar.valid || io.aw.valid).reduce(_ || _)
|
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val config_nchannels = Vec(channelConfigs.map(i => UInt(i)))(io.memory_channel_mux_select)
|
||||
assert(!mem_request || !io.mem_backup_en || config_nchannels === UInt(1),
|
||||
"Backup memory port only works when 1 memory channel is enabled")
|
||||
require(channelConfigs.sortWith(_ < _)(0) == 1,
|
||||
"Backup memory port requires a single memory port mux config")
|
||||
} else {
|
||||
io.mem <> mem_channels
|
||||
io.mem_backup.req.valid := Bool(false)
|
||||
}
|
||||
for ((nasti, tl) <- io.mem zip mem_ic.io.out)
|
||||
TopUtils.connectTilelinkNasti(nasti, tl)(outermostTLParams)
|
||||
}
|
||||
|
||||
@ -22,7 +22,6 @@ object TestBenchGeneration extends FileSystemUtilities {
|
||||
wire [`HTIF_WIDTH-1:0] htif_in_bits;
|
||||
wire htif_in_ready, htif_out_valid;
|
||||
wire [`HTIF_WIDTH-1:0] htif_out_bits;
|
||||
wire htif_out_stats;
|
||||
|
||||
wire mem_bk_in_valid;
|
||||
wire mem_bk_out_valid;
|
||||
@ -73,12 +72,6 @@ object TestBenchGeneration extends FileSystemUtilities {
|
||||
wire htif_out_valid_delay;
|
||||
wire htif_out_ready_delay;
|
||||
wire [`HTIF_WIDTH-1:0] htif_out_bits_delay;
|
||||
|
||||
wire htif_out_stats_delay;
|
||||
|
||||
wire mem_bk_out_ready_delay;
|
||||
wire mem_bk_in_valid_delay;
|
||||
wire mem_bk_out_valid_delay;
|
||||
|
||||
assign #0.1 htif_in_valid_delay = htif_in_valid;
|
||||
assign #0.1 htif_in_ready = htif_in_ready_delay;
|
||||
@ -87,12 +80,6 @@ object TestBenchGeneration extends FileSystemUtilities {
|
||||
assign #0.1 htif_out_valid = htif_out_valid_delay;
|
||||
assign #0.1 htif_out_ready_delay = htif_out_ready;
|
||||
assign #0.1 htif_out_bits = htif_out_bits_delay;
|
||||
|
||||
assign #0.1 htif_out_stats = htif_out_stats_delay;
|
||||
|
||||
assign #0.1 mem_bk_out_ready_delay = mem_bk_out_ready;
|
||||
assign #0.1 mem_bk_in_valid_delay = mem_bk_in_valid;
|
||||
assign #0.1 mem_bk_out_valid = mem_bk_out_valid_delay;
|
||||
"""
|
||||
|
||||
val nasti_delays = (0 until nMemChannel) map { i => s"""
|
||||
@ -216,8 +203,6 @@ object TestBenchGeneration extends FileSystemUtilities {
|
||||
|
||||
val instantiation = s"""
|
||||
`ifdef FPGA
|
||||
assign mem_bk_out_valid_delay = 1'b0;
|
||||
assign htif_out_stats_delay = 1'b0;
|
||||
assign htif_clk = clk;
|
||||
`endif
|
||||
|
||||
@ -231,25 +216,9 @@ object TestBenchGeneration extends FileSystemUtilities {
|
||||
`ifndef FPGA
|
||||
.io_host_clk(htif_clk),
|
||||
.io_host_clk_edge(),
|
||||
.io_host_debug_stats_csr(htif_out_stats_delay),
|
||||
|
||||
`ifdef MEM_BACKUP_EN
|
||||
.io_mem_backup_ctrl_en(1'b1),
|
||||
`else
|
||||
.io_mem_backup_ctrl_en(1'b0),
|
||||
`endif // MEM_BACKUP_EN
|
||||
.io_mem_backup_ctrl_in_valid(mem_bk_in_valid_delay),
|
||||
.io_mem_backup_ctrl_out_ready(mem_bk_out_ready_delay),
|
||||
.io_mem_backup_ctrl_out_valid(mem_bk_out_valid_delay),
|
||||
`else
|
||||
.io_host_clk (),
|
||||
.io_host_clk_edge (),
|
||||
.io_host_debug_stats_csr (),
|
||||
|
||||
.io_mem_backup_ctrl_en (1'b0),
|
||||
.io_mem_backup_ctrl_in_valid (1'b0),
|
||||
.io_mem_backup_ctrl_out_ready (1'b0),
|
||||
.io_mem_backup_ctrl_out_valid (),
|
||||
`endif // FPGA
|
||||
|
||||
.io_host_in_valid(htif_in_valid_delay),
|
||||
|
||||
@ -7,14 +7,6 @@ import cde.Parameters
|
||||
import junctions._
|
||||
import uncore._
|
||||
|
||||
class MemDessert(topParams: Parameters) extends Module {
|
||||
implicit val p = topParams
|
||||
val io = new MemDesserIO(p(HtifKey).width)
|
||||
val x = Module(new MemDesser(p(HtifKey).width))
|
||||
x.io.narrow <> io.narrow
|
||||
io.wide <> x.io.wide
|
||||
}
|
||||
|
||||
object VLSIUtils {
|
||||
def doOuterMemorySystemSerdes(
|
||||
llcs: Seq[NastiIO],
|
||||
@ -65,6 +57,30 @@ object VLSIUtils {
|
||||
}
|
||||
}
|
||||
|
||||
private def makeHTIFClockDivider(scr: SCRIO, host: HostIO, htifW: Int) = {
|
||||
val hio = Module((new SlowIO(512)) { Bits(width = htifW) })
|
||||
hio.io.set_divisor.valid := scr.wen && (scr.waddr === UInt(63))
|
||||
hio.io.set_divisor.bits := scr.wdata
|
||||
scr.rdata(63) := hio.io.divisor
|
||||
scr.allocate(63, "HTIF_IO_CLOCK_DIVISOR")
|
||||
host.clk := hio.io.clk_slow
|
||||
host.clk_edge := Reg(next=host.clk && !Reg(next=host.clk))
|
||||
hio
|
||||
}
|
||||
|
||||
def padOutHTIFWithDividedClock(
|
||||
htif: HostIO,
|
||||
scr: SCRIO,
|
||||
host: HostIO,
|
||||
htifW: Int) {
|
||||
val hio = makeHTIFClockDivider(scr, host, htifW)
|
||||
|
||||
hio.io.out_fast <> htif.out
|
||||
host.out <> hio.io.out_slow
|
||||
hio.io.in_slow <> host.in
|
||||
htif.in <> hio.io.in_fast
|
||||
}
|
||||
|
||||
def padOutHTIFWithDividedClock(
|
||||
htif: HostIO,
|
||||
scr: SCRIO,
|
||||
@ -72,11 +88,7 @@ object VLSIUtils {
|
||||
parent: MemBackupCtrlIO,
|
||||
host: HostIO,
|
||||
htifW: Int) {
|
||||
val hio = Module((new SlowIO(512)) { Bits(width = htifW+1) })
|
||||
hio.io.set_divisor.valid := scr.wen && (scr.waddr === UInt(63))
|
||||
hio.io.set_divisor.bits := scr.wdata
|
||||
scr.rdata(63) := hio.io.divisor
|
||||
scr.allocate(63, "HTIF_IO_CLOCK_DIVISOR")
|
||||
val hio = makeHTIFClockDivider(scr, host, htifW+1)
|
||||
|
||||
hio.io.out_fast.valid := htif.out.valid || child.req.valid
|
||||
hio.io.out_fast.bits := Cat(htif.out.valid, Mux(htif.out.valid, htif.out.bits, child.req.bits))
|
||||
@ -96,7 +108,5 @@ object VLSIUtils {
|
||||
htif.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htifW)
|
||||
htif.in.bits := hio.io.in_fast.bits
|
||||
hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htifW), Bool(true), htif.in.ready)
|
||||
host.clk := hio.io.clk_slow
|
||||
host.clk_edge := Reg(next=host.clk && !Reg(next=host.clk))
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user