riscv/rocket-chip
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WIP on new memory map

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Andrew Waterman
2016-04-27 14:57:54 -07:00
parent 48170fd9aa
commit 1f211b37df
17 changed files with 110 additions and 466 deletions
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@ -365,7 +365,6 @@ Top.DefaultVLSIConfig.conf file:
Top.DefaultVLSIConfig.prm
Top.DefaultVLSIConfig.v
consts.DefaultVLSIConfig.vh
memdessertMemDessert.DefaultVLSIConfig.v
$ cat $ROCKETCHIP/vsim/generated-src/*.conf
name MetadataArray_tag_arr depth 128 width 84 ports mwrite,read mask_gran 21
name ICache_tag_array depth 128 width 38 ports mrw mask_gran 19