riscv/rocket-chip
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fuzzer: allow fuzzing range to be overridden

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This commit is contained in:
Henry Cook
2017-05-03 15:29:14 -07:00
parent cd547fabbd
commit 1f1240baf1
2 changed files with 11 additions and 6 deletions
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12
src/main/scala/uncore/axi4/Test.scala
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@@ -62,10 +62,14 @@ class AXI4FullFuzzRAMTest(implicit p: Parameters) extends UnitTest(500000) {
io.finished := dut.io.finished io.finished := dut.io.finished
} }
class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule trait HasFuzzTarget {
val fuzzAddr = AddressSet(0x0, 0xfff)
}
class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule with HasFuzzTarget
{ {
val node = AXI4OutputNode() val node = AXI4OutputNode()
val fuzz = LazyModule(new TLFuzzer(5000)) val fuzz = LazyModule(new TLFuzzer(5000, overrideAddress = Some(fuzzAddr)))
val model = LazyModule(new TLRAMModel("AXI4FuzzMaster")) val model = LazyModule(new TLRAMModel("AXI4FuzzMaster"))
model.node := fuzz.node model.node := fuzz.node
@@ -88,11 +92,11 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
} }
} }
class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTarget
{ {
val node = AXI4InputNode() val node = AXI4InputNode()
val xbar = LazyModule(new TLXbar) val xbar = LazyModule(new TLXbar)
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0xfff))) val ram = LazyModule(new TLRAM(fuzzAddr))
val error= LazyModule(new TLError(Seq(AddressSet(0x1800, 0xff)))) val error= LazyModule(new TLError(Seq(AddressSet(0x1800, 0xff))))
ram.node := TLFragmenter(4, 16)(xbar.node) ram.node := TLFragmenter(4, 16)(xbar.node)

5
src/main/scala/uncore/tilelink2/Fuzzer.scala
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@@ -82,7 +82,8 @@ class TLFuzzer(
(wide: Int, increment: Bool, abs_values: Int) => (wide: Int, increment: Bool, abs_values: Int) =>
LFSRNoiseMaker(wide=wide, increment=increment) LFSRNoiseMaker(wide=wide, increment=increment)
}, },
noModify: Boolean = false)(implicit p: Parameters) extends LazyModule noModify: Boolean = false,
overrideAddress: Option[AddressSet] = None)(implicit p: Parameters) extends LazyModule
{ {
val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,inFlight))) val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,inFlight)))
@@ -96,7 +97,7 @@ class TLFuzzer(
val edge = node.edgesOut(0) val edge = node.edgesOut(0)
// Extract useful parameters from the TL edge // Extract useful parameters from the TL edge
val endAddress = edge.manager.maxAddress + 1 val endAddress = overrideAddress.map(_.max).getOrElse(edge.manager.maxAddress)
val maxTransfer = edge.manager.maxTransfer val maxTransfer = edge.manager.maxTransfer
val beatBytes = edge.manager.beatBytes val beatBytes = edge.manager.beatBytes
val maxLgBeats = log2Up(maxTransfer/beatBytes) val maxLgBeats = log2Up(maxTransfer/beatBytes)