diff --git a/vsrc/DebugTransportModuleJtag.v b/vsrc/DebugTransportModuleJtag.v
index 7d3348d5..da74adde 100755
--- a/vsrc/DebugTransportModuleJtag.v
+++ b/vsrc/DebugTransportModuleJtag.v
@@ -156,10 +156,9 @@ module DebugTransportModuleJtag (
    //busy, dtm_resp* is only valid during CAPTURE_DR,
    //      so these signals should only be used at that time.
    // This assumes there is only one transaction in flight at a time.
-   assign busy = (busyReg & ~dtm_resp_valid); // stickyBusyReg;
+   assign busy = (busyReg & ~dtm_resp_valid) | stickyBusyReg;
    // This is needed especially for the first request.
-   assign nonzeroResp = (dtm_resp_valid ? |{dtm_resp_bits[DEBUG_OP_BITS-1:0]} : 1'b0);
-   //stickyNonzeroRespReg;
+   assign nonzeroResp = (dtm_resp_valid ? | {dtm_resp_bits[DEBUG_OP_BITS-1:0]} : 1'b0) | stickyNonzeroRespReg;
    
    // Interface to DM.
    // Note that this means dtm_resp_bits must only be used during CAPTURE_DR.