riscv/rocket-chip
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[rocket] add TODO for single cycle ack

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This commit is contained in:
Henry Cook 2016-11-17 15:48:33 -08:00
parent 94086f2270
commit 1ddccb1b33
1 changed files with 2 additions and 3 deletions
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src/main/scala/rocket/dcache.scala
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@ -330,10 +330,9 @@ class DCache(maxUncachedInFlight: Int = 2)(implicit val p: Parameters) extends L
assert(cached_grant_wait, "A GrantData was unexpected by the dcache.") assert(cached_grant_wait, "A GrantData was unexpected by the dcache.")
when(d_last) { cached_grant_wait := false } when(d_last) { cached_grant_wait := false }
} .elsewhen (grantIsUncached) { } .elsewhen (grantIsUncached) {
// TODO this requires that uncached accesses only take a single beat
val id = tl_out.d.bits.source val id = tl_out.d.bits.source
val req = uncachedReqs(id) val req = uncachedReqs(id)
assert(uncachedInFlight(id), "An AccessAck was unexpected by the dcache.") assert(uncachedInFlight(id), "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle!
when(d_last) { uncachedInFlight(id) := false } when(d_last) { uncachedInFlight(id) := false }
s2_data := tl_out.d.bits.data s2_data := tl_out.d.bits.data
s2_req.cmd := req.cmd s2_req.cmd := req.cmd
@ -341,7 +340,7 @@ class DCache(maxUncachedInFlight: Int = 2)(implicit val p: Parameters) extends L
s2_req.tag := req.tag s2_req.tag := req.tag
s2_req.addr := Cat(s1_paddr >> wordOffBits /* don't-care */, req.addr(wordOffBits-1, 0)) s2_req.addr := Cat(s1_paddr >> wordOffBits /* don't-care */, req.addr(wordOffBits-1, 0))
} .elsewhen (grantIsVoluntary) { } .elsewhen (grantIsVoluntary) {
assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle!
release_ack_wait := false release_ack_wait := false
} }
} }