Merge pull request #957 from freechipsproject/param_jtag_vpi
jtag_vpi: Use Parameterized Black Box
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commit
1db4b3be9a
@ -3,6 +3,7 @@
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package freechips.rocketchip.devices.debug
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package freechips.rocketchip.devices.debug
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import Chisel._
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import Chisel._
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import chisel3.core.{IntParam}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.coreplex.HasPeripheryBus
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import freechips.rocketchip.coreplex.HasPeripheryBus
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.devices.tilelink._
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@ -37,12 +38,12 @@ trait HasPeripheryDebugBundle {
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val debug: DebugIO
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val debug: DebugIO
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def connectDebug(c: Clock, r: Bool, out: Bool) {
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def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2) {
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debug.clockeddmi.foreach { d =>
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debug.clockeddmi.foreach { d =>
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val dtm = Module(new SimDTM).connect(c, r, d, out)
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val dtm = Module(new SimDTM).connect(c, r, d, out)
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}
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}
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debug.systemjtag.foreach { sj =>
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debug.systemjtag.foreach { sj =>
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val jtag = Module(new JTAGVPI).connect(sj.jtag, sj.reset, r, out)
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val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out)
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sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
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sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
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}
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}
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}
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}
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@ -100,7 +101,9 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
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}
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}
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}
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}
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class JTAGVPI(implicit val p: Parameters) extends BlackBox {
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class JTAGVPI(tckHalfPeriod: Int = 2, cmdDelay: Int = 2)(implicit val p: Parameters)
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extends BlackBox ( Map ("TCK_HALF_PERIOD" -> IntParam(tckHalfPeriod),
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"CMD_DELAY" -> IntParam(cmdDelay))) {
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val io = new Bundle {
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val io = new Bundle {
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val jtag = new JTAGIO(hasTRSTn = false)
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val jtag = new JTAGIO(hasTRSTn = false)
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val enable = Bool(INPUT)
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val enable = Bool(INPUT)
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