riscv/rocket-chip
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use UFix instead of Bits for arithmetic

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Andrew Waterman 2013-05-18 00:45:29 -07:00
parent dfa7a03f73
commit 1dab984231
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -669,7 +669,7 @@ class AMOALU(implicit conf: DCacheConfig) extends Component {
val word = io.typ === MT_W || io.typ === MT_WU || io.typ === MT_B || io.typ === MT_BU val word = io.typ === MT_W || io.typ === MT_WU || io.typ === MT_B || io.typ === MT_BU
val mask = Fix(-1,64) ^ (io.addr(2) << 31) val mask = Fix(-1,64) ^ (io.addr(2) << 31)
val adder_out = (io.lhs & mask) + (io.rhs & mask) val adder_out = (io.lhs & mask).toUFix + (io.rhs & mask)
val cmp_lhs = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63)) val cmp_lhs = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63))
val cmp_rhs = Mux(word && !io.addr(2), io.rhs(31), io.rhs(63)) val cmp_rhs = Mux(word && !io.addr(2), io.rhs(31), io.rhs(63))