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new chisel version jar and find and replace INPUT and OUTPUT

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This commit is contained in:
Henry Cook 2012-01-18 10:28:48 -08:00
parent e4cf6391d7
commit 1d76255dc1
18 changed files with 372 additions and 358 deletions
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18
rocket/src/main/scala/arbiter.scala
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@ -6,16 +6,16 @@ import Constants._;
class ioMem() extends Bundle
{
val req_val = Bool('output);
val req_rdy = Bool('input);
val req_rw = Bool('output);
val req_addr = UFix(PADDR_BITS - OFFSET_BITS, 'output);
val req_wdata = Bits(MEM_DATA_BITS, 'output);
val req_tag = Bits(MEM_TAG_BITS, 'output);
val req_val = Bool(OUTPUT);
val req_rdy = Bool(INPUT);
val req_rw = Bool(OUTPUT);
val req_addr = UFix(PADDR_BITS - OFFSET_BITS, OUTPUT);
val req_wdata = Bits(MEM_DATA_BITS, OUTPUT);
val req_tag = Bits(MEM_TAG_BITS, OUTPUT);
val resp_val = Bool('input);
val resp_tag = Bits(MEM_TAG_BITS, 'input);
val resp_data = Bits(MEM_DATA_BITS, 'input);
val resp_val = Bool(INPUT);
val resp_tag = Bits(MEM_TAG_BITS, INPUT);
val resp_data = Bits(MEM_DATA_BITS, INPUT);
}
class ioMemArbiter extends Bundle() {

14
rocket/src/main/scala/cpu.scala
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@ -6,21 +6,21 @@ import Constants._;
class ioDebug(view: List[String] = null) extends Bundle(view)
{
val error_mode = Bool('output);
val error_mode = Bool(OUTPUT);
}
class ioHost(view: List[String] = null) extends Bundle(view)
{
val from_wen = Bool('input);
val from = Bits(64, 'input);
val to = Bits(64, 'output);
val from_wen = Bool(INPUT);
val from = Bits(64, INPUT);
val to = Bits(64, OUTPUT);
}
class ioConsole(view: List[String] = null) extends Bundle(view)
{
val rdy = Bool('input);
val valid = Bool('output);
val bits = Bits(8, 'output);
val rdy = Bool(INPUT);
val valid = Bool(OUTPUT);
val bits = Bits(8, OUTPUT);
}
class ioRocket extends Bundle()

134
rocket/src/main/scala/ctrl.scala
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@ -9,67 +9,67 @@ import Instructions._
class ioCtrlDpath extends Bundle()
{
// outputs to datapath
val sel_pc = UFix(4, 'output);
val wen_btb = Bool('output);
val clr_btb = Bool('output);
val stallf = Bool('output);
val stalld = Bool('output);
val killf = Bool('output);
val killd = Bool('output);
val killx = Bool('output);
val killm = Bool('output);
val ren2 = Bool('output);
val ren1 = Bool('output);
val sel_alu2 = UFix(2, 'output);
val sel_alu1 = Bool('output);
val fn_dw = Bool('output);
val fn_alu = UFix(4, 'output);
val mul_val = Bool('output);
val mul_fn = UFix(2, 'output);
val mul_wb = Bool('output);
val div_val = Bool('output);
val div_fn = UFix(2, 'output);
val div_wb = Bool('output);
val sel_wa = Bool('output);
val sel_wb = UFix(3, 'output);
val ren_pcr = Bool('output);
val wen_pcr = Bool('output);
val id_eret = Bool('output);
val wb_eret = Bool('output);
val mem_load = Bool('output);
val wen = Bool('output);
val sel_pc = UFix(4, OUTPUT);
val wen_btb = Bool(OUTPUT);
val clr_btb = Bool(OUTPUT);
val stallf = Bool(OUTPUT);
val stalld = Bool(OUTPUT);
val killf = Bool(OUTPUT);
val killd = Bool(OUTPUT);
val killx = Bool(OUTPUT);
val killm = Bool(OUTPUT);
val ren2 = Bool(OUTPUT);
val ren1 = Bool(OUTPUT);
val sel_alu2 = UFix(2, OUTPUT);
val sel_alu1 = Bool(OUTPUT);
val fn_dw = Bool(OUTPUT);
val fn_alu = UFix(4, OUTPUT);
val mul_val = Bool(OUTPUT);
val mul_fn = UFix(2, OUTPUT);
val mul_wb = Bool(OUTPUT);
val div_val = Bool(OUTPUT);
val div_fn = UFix(2, OUTPUT);
val div_wb = Bool(OUTPUT);
val sel_wa = Bool(OUTPUT);
val sel_wb = UFix(3, OUTPUT);
val ren_pcr = Bool(OUTPUT);
val wen_pcr = Bool(OUTPUT);
val id_eret = Bool(OUTPUT);
val wb_eret = Bool(OUTPUT);
val mem_load = Bool(OUTPUT);
val wen = Bool(OUTPUT);
// instruction in execute is an unconditional jump
val ex_jmp = Bool('output);
val ex_jr = Bool('output);
val ex_jmp = Bool(OUTPUT);
val ex_jr = Bool(OUTPUT);
// enable/disable interrupts
val irq_enable = Bool('output);
val irq_disable = Bool('output);
val irq_enable = Bool(OUTPUT);
val irq_disable = Bool(OUTPUT);
// exception handling
val exception = Bool('output);
val cause = UFix(5,'output);
val badvaddr_wen = Bool('output); // high for a load/store access fault
val exception = Bool(OUTPUT);
val cause = UFix(5,OUTPUT);
val badvaddr_wen = Bool(OUTPUT); // high for a load/store access fault
// inputs from datapath
val xcpt_ma_inst = Bool('input); // high on a misaligned/illegal virtual PC
val btb_hit = Bool('input);
val btb_match = Bool('input);
val inst = Bits(32, 'input);
val br_eq = Bool('input);
val br_lt = Bool('input);
val br_ltu = Bool('input);
val div_rdy = Bool('input);
val div_result_val = Bool('input);
val mul_rdy = Bool('input);
val mul_result_val = Bool('input);
val mem_lu_bypass = Bool('input);
val ex_waddr = UFix(5,'input); // write addr from execute stage
val mem_waddr = UFix(5,'input); // write addr from memory stage
val wb_waddr = UFix(5,'input); // write addr from writeback stage
val status = Bits(17, 'input);
val sboard_clr = Bool('input);
val sboard_clra = UFix(5, 'input);
val mem_valid = Bool('input); // high if there's a valid (not flushed) instruction in mem stage
val irq_timer = Bool('input);
val irq_ipi = Bool('input);
val xcpt_ma_inst = Bool(INPUT); // high on a misaligned/illegal virtual PC
val btb_hit = Bool(INPUT);
val btb_match = Bool(INPUT);
val inst = Bits(32, INPUT);
val br_eq = Bool(INPUT);
val br_lt = Bool(INPUT);
val br_ltu = Bool(INPUT);
val div_rdy = Bool(INPUT);
val div_result_val = Bool(INPUT);
val mul_rdy = Bool(INPUT);
val mul_result_val = Bool(INPUT);
val mem_lu_bypass = Bool(INPUT);
val ex_waddr = UFix(5,INPUT); // write addr from execute stage
val mem_waddr = UFix(5,INPUT); // write addr from memory stage
val wb_waddr = UFix(5,INPUT); // write addr from writeback stage
val status = Bits(17, INPUT);
val sboard_clr = Bool(INPUT);
val sboard_clra = UFix(5, INPUT);
val mem_valid = Bool(INPUT); // high if there's a valid (not flushed) instruction in mem stage
val irq_timer = Bool(INPUT);
val irq_ipi = Bool(INPUT);
}
class ioCtrlAll extends Bundle()
@ -78,16 +78,16 @@ class ioCtrlAll extends Bundle()
val console = new ioConsole(List("rdy"));
val imem = new ioImem(List("req_val", "resp_val")).flip();
val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_replay", "resp_nack")).flip();
val dtlb_val = Bool('output);
val dtlb_kill = Bool('output);
val dtlb_rdy = Bool('input);
val dtlb_miss = Bool('input);
val flush_inst = Bool('output);
val xcpt_dtlb_ld = Bool('input);
val xcpt_dtlb_st = Bool('input);
val xcpt_itlb = Bool('input);
val xcpt_ma_ld = Bool('input);
val xcpt_ma_st = Bool('input);
val dtlb_val = Bool(OUTPUT);
val dtlb_kill = Bool(OUTPUT);
val dtlb_rdy = Bool(INPUT);
val dtlb_miss = Bool(INPUT);
val flush_inst = Bool(OUTPUT);
val xcpt_dtlb_ld = Bool(INPUT);
val xcpt_dtlb_st = Bool(INPUT);
val xcpt_itlb = Bool(INPUT);
val xcpt_ma_ld = Bool(INPUT);
val xcpt_ma_st = Bool(INPUT);
}
class rocketCtrl extends Component

28
rocket/src/main/scala/ctrl_util.scala
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@ -6,16 +6,16 @@ import Constants._;
class ioCtrlSboard extends Bundle()
{
val clr = Bool('input);
val clra = UFix(5, 'input);
val set = Bool('input);
val seta = UFix(5, 'input);
val raddra = UFix(5, 'input);
val raddrb = UFix(5, 'input);
val raddrc = UFix(5, 'input);
val stalla = Bool('output);
val stallb = Bool('output);
val stallc = Bool('output);
val clr = Bool(INPUT);
val clra = UFix(5, INPUT);
val set = Bool(INPUT);
val seta = UFix(5, INPUT);
val raddra = UFix(5, INPUT);
val raddrb = UFix(5, INPUT);
val raddrc = UFix(5, INPUT);
val stalla = Bool(OUTPUT);
val stallb = Bool(OUTPUT);
val stallc = Bool(OUTPUT);
}
class rocketCtrlSboard extends Component
@ -34,10 +34,10 @@ class rocketCtrlSboard extends Component
class ioCtrlCnt extends Bundle()
{
val enq = Bool('input);
val deq = Bool('input);
val empty = Bool('output);
val full = Bool('output);
val enq = Bool(INPUT);
val deq = Bool(INPUT);
val empty = Bool(OUTPUT);
val full = Bool(OUTPUT);
}
class rocketCtrlCnt(n_bits: Int, limit: Int) extends Component

74
rocket/src/main/scala/dcache.scala
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@ -7,37 +7,37 @@ import scala.math._;
// interface between D$ and processor/DTLB
class ioDmem(view: List[String] = null) extends Bundle(view) {
val req_kill = Bool('input);
val req_val = Bool('input);
val req_rdy = Bool('output);
val req_cmd = Bits(4, 'input);
val req_type = Bits(3, 'input);
val req_idx = Bits(PGIDX_BITS, 'input);
val req_ppn = Bits(PPN_BITS, 'input);
val req_data = Bits(64, 'input);
val req_tag = Bits(DCACHE_TAG_BITS, 'input);
val xcpt_ma_ld = Bool('output); // misaligned load
val xcpt_ma_st = Bool('output); // misaligned store
val resp_miss = Bool('output);
val resp_nack = Bool('output);
val resp_val = Bool('output);
val resp_replay = Bool('output);
val resp_data = Bits(64, 'output);
val resp_data_subword = Bits(64, 'output);
val resp_tag = Bits(DCACHE_TAG_BITS, 'output);
val req_kill = Bool(INPUT);
val req_val = Bool(INPUT);
val req_rdy = Bool(OUTPUT);
val req_cmd = Bits(4, INPUT);
val req_type = Bits(3, INPUT);
val req_idx = Bits(PGIDX_BITS, INPUT);
val req_ppn = Bits(PPN_BITS, INPUT);
val req_data = Bits(64, INPUT);
val req_tag = Bits(DCACHE_TAG_BITS, INPUT);
val xcpt_ma_ld = Bool(OUTPUT); // misaligned load
val xcpt_ma_st = Bool(OUTPUT); // misaligned store
val resp_miss = Bool(OUTPUT);
val resp_nack = Bool(OUTPUT);
val resp_val = Bool(OUTPUT);
val resp_replay = Bool(OUTPUT);
val resp_data = Bits(64, OUTPUT);
val resp_data_subword = Bits(64, OUTPUT);
val resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT);
}
// interface between D$ and next level in memory hierarchy
class ioDcache(view: List[String] = null) extends Bundle(view) {
val req_addr = UFix(PADDR_BITS - OFFSET_BITS, 'input);
val req_tag = UFix(DMEM_TAG_BITS, 'input);
val req_val = Bool('input);
val req_rdy = Bool('output);
val req_wdata = Bits(MEM_DATA_BITS, 'input);
val req_rw = Bool('input);
val resp_data = Bits(MEM_DATA_BITS, 'output);
val resp_tag = Bits(DMEM_TAG_BITS, 'output);
val resp_val = Bool('output);
val req_addr = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
val req_tag = UFix(DMEM_TAG_BITS, INPUT);
val req_val = Bool(INPUT);
val req_rdy = Bool(OUTPUT);
val req_wdata = Bits(MEM_DATA_BITS, INPUT);
val req_rw = Bool(INPUT);
val resp_data = Bits(MEM_DATA_BITS, OUTPUT);
val resp_tag = Bits(DMEM_TAG_BITS, OUTPUT);
val resp_val = Bool(OUTPUT);
}
class ioDCacheDM extends Bundle() {
@ -47,11 +47,11 @@ class ioDCacheDM extends Bundle() {
class rocketDCacheStoreGen extends Component {
val io = new Bundle {
val req_type = Bits(3, 'input);
val req_addr_lsb = Bits(3, 'input);
val req_data = Bits(64, 'input);
val store_wmask = Bits(64, 'output);
val store_data = Bits(64, 'output);
val req_type = Bits(3, INPUT);
val req_addr_lsb = Bits(3, INPUT);
val req_data = Bits(64, INPUT);
val store_wmask = Bits(64, OUTPUT);
val store_data = Bits(64, OUTPUT);
}
// generate write mask and store data signals based on store type and address LSBs
@ -481,11 +481,11 @@ class rocketDCacheDM(lines: Int) extends Component {
class rocketDCacheAmoALU extends Component {
val io = new Bundle {
val cmd = Bits(4, 'input);
val wmask = Bits(8, 'input);
val lhs = UFix(64, 'input);
val rhs = UFix(64, 'input);
val result = UFix(64, 'output);
val cmd = Bits(4, INPUT);
val wmask = Bits(8, INPUT);
val lhs = UFix(64, INPUT);
val rhs = UFix(64, INPUT);
val result = UFix(64, OUTPUT);
}
// val signed_cmp = (op === M_XA_MIN) || (op === M_XA_MAX);

42
rocket/src/main/scala/divider.scala
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@ -6,33 +6,33 @@ import Constants._;
class ioDivider(width: Int) extends Bundle {
// requests
val div_val = Bool('input);
val div_kill = Bool('input);
val div_rdy = Bool('output);
val dw = UFix(1, 'input);
val div_fn = UFix(2, 'input);
val div_waddr = UFix(5, 'input);
val dpath_rs1 = Bits(width, 'input);
val dpath_rs2 = Bits(width, 'input);
val div_val = Bool(INPUT);
val div_kill = Bool(INPUT);
val div_rdy = Bool(OUTPUT);
val dw = UFix(1, INPUT);
val div_fn = UFix(2, INPUT);
val div_waddr = UFix(5, INPUT);
val dpath_rs1 = Bits(width, INPUT);
val dpath_rs2 = Bits(width, INPUT);
// responses
val div_result_bits = Bits(width, 'output);
val div_result_tag = UFix(5, 'output);
val div_result_val = Bool('output);
val div_result_rdy = Bool('input);
val div_result_bits = Bits(width, OUTPUT);
val div_result_tag = UFix(5, OUTPUT);
val div_result_val = Bool(OUTPUT);
val div_result_rdy = Bool(INPUT);
}
// class ioDivider extends Bundle {
// // requests
// val req_val = Bool('input);
// val req_rdy = Bool('output);
// val req_fn = UFix(3, 'input);
// val req_tag = UFix(5, 'input);
// val req_rs1 = Bits(64, 'input);
// val req_rs2 = Bits(64, 'input);
// val req_val = Bool(INPUT);
// val req_rdy = Bool(OUTPUT);
// val req_fn = UFix(3, INPUT);
// val req_tag = UFix(5, INPUT);
// val req_rs1 = Bits(64, INPUT);
// val req_rs2 = Bits(64, INPUT);
// // responses
// val resp_val = Bool('output);
// val resp_data = Bits(64, 'output);
// val resp_tag = UFix(5, 'output);
// val resp_val = Bool(OUTPUT);
// val resp_data = Bits(64, OUTPUT);
// val resp_tag = UFix(5, OUTPUT);
// }
class rocketDivider(width : Int) extends Component {

26
rocket/src/main/scala/dpath.scala
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@ -7,21 +7,21 @@ import Instructions._
class ioDpathDmem extends Bundle()
{
val req_addr = UFix(VADDR_BITS, 'output);
val req_tag = UFix(CPU_TAG_BITS, 'output);
val req_data = Bits(64, 'output);
val resp_val = Bool('input);
val resp_miss = Bool('input);
val resp_replay = Bool('input);
val resp_tag = Bits(CPU_TAG_BITS, 'input);
val resp_data = Bits(64, 'input);
val resp_data_subword = Bits(64, 'input);
val req_addr = UFix(VADDR_BITS, OUTPUT);
val req_tag = UFix(CPU_TAG_BITS, OUTPUT);
val req_data = Bits(64, OUTPUT);
val resp_val = Bool(INPUT);
val resp_miss = Bool(INPUT);
val resp_replay = Bool(INPUT);
val resp_tag = Bits(CPU_TAG_BITS, INPUT);
val resp_data = Bits(64, INPUT);
val resp_data_subword = Bits(64, INPUT);
}
class ioDpathImem extends Bundle()
{
val req_addr = UFix(VADDR_BITS, 'output);
val resp_data = Bits(32, 'input);
val req_addr = UFix(VADDR_BITS, OUTPUT);
val resp_data = Bits(32, INPUT);
}
class ioDpathAll extends Bundle()
@ -32,8 +32,8 @@ class ioDpathAll extends Bundle()
val debug = new ioDebug();
val dmem = new ioDpathDmem();
val imem = new ioDpathImem();
val ptbr_wen = Bool('output);
val ptbr = UFix(PADDR_BITS, 'output);
val ptbr_wen = Bool(OUTPUT);
val ptbr = UFix(PADDR_BITS, OUTPUT);
}
class rocketDpath extends Component

14
rocket/src/main/scala/dpath_alu.scala
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@ -8,13 +8,13 @@ import Constants._
import Instructions._
class ioALU extends Bundle(){
val dw = UFix(1, 'input);
val fn = UFix(4, 'input);
val shamt = UFix(6, 'input);
val in2 = UFix(64, 'input);
val in1 = UFix(64, 'input);
val out = UFix(64, 'output);
val adder_out = UFix(64, 'output);
val dw = UFix(1, INPUT);
val fn = UFix(4, INPUT);
val shamt = UFix(6, INPUT);
val in2 = UFix(64, INPUT);
val in1 = UFix(64, INPUT);
val out = UFix(64, OUTPUT);
val adder_out = UFix(64, OUTPUT);
}
class rocketDpathALU extends Component

56
rocket/src/main/scala/dpath_util.scala
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@ -8,13 +8,13 @@ import scala.math._;
class ioDpathBTB extends Bundle()
{
val current_pc4 = UFix(VADDR_BITS, 'input);
val hit = Bool('output);
val target = UFix(VADDR_BITS, 'output);
val wen = Bool('input);
val clr = Bool('input);
val correct_pc4 = UFix(VADDR_BITS, 'input);
val correct_target = UFix(VADDR_BITS, 'input);
val current_pc4 = UFix(VADDR_BITS, INPUT);
val hit = Bool(OUTPUT);
val target = UFix(VADDR_BITS, OUTPUT);
val wen = Bool(INPUT);
val clr = Bool(INPUT);
val correct_pc4 = UFix(VADDR_BITS, INPUT);
val correct_target = UFix(VADDR_BITS, INPUT);
}
// basic direct-mapped branch target buffer
@ -45,21 +45,21 @@ class ioDpathPCR extends Bundle()
val r = new ioReadPort();
val w = new ioWritePort();
val status = Bits(17, 'output);
val ptbr = UFix(PADDR_BITS, 'output);
val evec = UFix(VADDR_BITS, 'output);
val exception = Bool('input);
val cause = UFix(5, 'input);
val badvaddr_wen = Bool('input);
val pc = UFix(VADDR_BITS, 'input);
val eret = Bool('input);
val ei = Bool('input);
val di = Bool('input);
val ptbr_wen = Bool('output);
val irq_timer = Bool('output);
val irq_ipi = Bool('output);
val console_data = Bits(8, 'output);
val console_val = Bool('output);
val status = Bits(17, OUTPUT);
val ptbr = UFix(PADDR_BITS, OUTPUT);
val evec = UFix(VADDR_BITS, OUTPUT);
val exception = Bool(INPUT);
val cause = UFix(5, INPUT);
val badvaddr_wen = Bool(INPUT);
val pc = UFix(VADDR_BITS, INPUT);
val eret = Bool(INPUT);
val ei = Bool(INPUT);
val di = Bool(INPUT);
val ptbr_wen = Bool(OUTPUT);
val irq_timer = Bool(OUTPUT);
val irq_ipi = Bool(OUTPUT);
val console_data = Bits(8, OUTPUT);
val console_val = Bool(OUTPUT);
}
class rocketDpathPCR extends Component
@ -203,16 +203,16 @@ class rocketDpathPCR extends Component
class ioReadPort extends Bundle()
{
val addr = UFix(5, 'input);
val en = Bool('input);
val data = Bits(64, 'output);
val addr = UFix(5, INPUT);
val en = Bool(INPUT);
val data = Bits(64, OUTPUT);
}
class ioWritePort extends Bundle()
{
val addr = UFix(5, 'input);
val en = Bool('input);
val data = Bits(64, 'input);
val addr = UFix(5, INPUT);
val en = Bool(INPUT);
val data = Bits(64, INPUT);
}
class ioRegfile extends Bundle()

26
rocket/src/main/scala/dtlb.scala
View File

@ -10,22 +10,22 @@ import scala.math._;
class ioDTLB_CPU(view: List[String] = null) extends Bundle(view)
{
// status bits (from PCR), to check current permission and whether VM is enabled
val status = Bits(17, 'input);
val status = Bits(17, INPUT);
// invalidate all TLB entries
val invalidate = Bool('input);
val invalidate = Bool(INPUT);
// lookup requests
val req_val = Bool('input);
val req_kill = Bool('input);
val req_cmd = Bits(4, 'input); // load/store/amo
val req_rdy = Bool('output);
val req_asid = Bits(ASID_BITS, 'input);
val req_vpn = UFix(VPN_BITS, 'input);
val req_val = Bool(INPUT);
val req_kill = Bool(INPUT);
val req_cmd = Bits(4, INPUT); // load/store/amo
val req_rdy = Bool(OUTPUT);
val req_asid = Bits(ASID_BITS, INPUT);
val req_vpn = UFix(VPN_BITS, INPUT);
// lookup responses
val resp_miss = Bool('output);
// val resp_val = Bool('output);
val resp_ppn = UFix(PPN_BITS, 'output);
val xcpt_ld = Bool('output);
val xcpt_st = Bool('output);
val resp_miss = Bool(OUTPUT);
// val resp_val = Bool(OUTPUT);
val resp_ppn = UFix(PPN_BITS, OUTPUT);
val xcpt_ld = Bool(OUTPUT);
val xcpt_st = Bool(OUTPUT);
}
class ioDTLB extends Bundle

24
rocket/src/main/scala/icache.scala
View File

@ -8,23 +8,23 @@ import scala.math._;
// interface between I$ and pipeline/ITLB (32 bits wide)
class ioImem(view: List[String] = null) extends Bundle (view)
{
val invalidate = Bool('input);
val itlb_miss = Bool('input);
val req_val = Bool('input);
val req_idx = Bits(PGIDX_BITS, 'input);
val req_ppn = Bits(PPN_BITS, 'input);
val resp_data = Bits(32, 'output);
val resp_val = Bool('output);
val invalidate = Bool(INPUT);
val itlb_miss = Bool(INPUT);
val req_val = Bool(INPUT);
val req_idx = Bits(PGIDX_BITS, INPUT);
val req_ppn = Bits(PPN_BITS, INPUT);
val resp_data = Bits(32, OUTPUT);
val resp_val = Bool(OUTPUT);
}
// interface between I$ and memory (128 bits wide)
class ioIcache(view: List[String] = null) extends Bundle (view)
{
val req_addr = UFix(PADDR_BITS - OFFSET_BITS, 'input);
val req_val = Bool('input);
val req_rdy = Bool('output);
val resp_data = Bits(MEM_DATA_BITS, 'output);
val resp_val = Bool('output);
val req_addr = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
val req_val = Bool(INPUT);
val req_rdy = Bool(OUTPUT);
val resp_data = Bits(MEM_DATA_BITS, OUTPUT);
val resp_val = Bool(OUTPUT);
}
class ioICacheDM extends Bundle()

14
rocket/src/main/scala/icache_prefetch.scala
View File

@ -7,13 +7,13 @@ import scala.math._;
class ioIPrefetcherMem(view: List[String] = null) extends Bundle (view)
{
val req_addr = UFix(PADDR_BITS - OFFSET_BITS, 'output);
val req_val = Bool('output);
val req_rdy = Bool('input);
val req_tag = Bits(IMEM_TAG_BITS, 'output);
val resp_data = Bits(MEM_DATA_BITS, 'input);
val resp_val = Bool('input);
val resp_tag = Bits(IMEM_TAG_BITS, 'input);
val req_addr = UFix(PADDR_BITS - OFFSET_BITS, OUTPUT);
val req_val = Bool(OUTPUT);
val req_rdy = Bool(INPUT);
val req_tag = Bits(IMEM_TAG_BITS, OUTPUT);
val resp_data = Bits(MEM_DATA_BITS, INPUT);
val resp_val = Bool(INPUT);
val resp_tag = Bits(IMEM_TAG_BITS, INPUT);
}
class ioIPrefetcher extends Bundle() {

50
rocket/src/main/scala/itlb.scala
View File

@ -7,15 +7,15 @@ import Constants._;
import scala.math._;
class ioCAM(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle {
val clear = Bool('input);
val tag = Bits(tag_bits, 'input);
val hit = Bool('output);
val hit_addr = UFix(addr_bits, 'output);
val valid_bits = Bits(entries, 'output);
val clear = Bool(INPUT);
val tag = Bits(tag_bits, INPUT);
val hit = Bool(OUTPUT);
val hit_addr = UFix(addr_bits, OUTPUT);
val valid_bits = Bits(entries, OUTPUT);
val write = Bool('input);
val write_tag = Bits(tag_bits, 'input);
val write_addr = UFix(addr_bits, 'input);
val write = Bool(INPUT);
val write_tag = Bits(tag_bits, INPUT);
val write_addr = UFix(addr_bits, INPUT);
}
class rocketCAM(entries: Int, tag_bits: Int) extends Component {
@ -53,33 +53,33 @@ class rocketCAM(entries: Int, tag_bits: Int) extends Component {
class ioTLB_PTW extends Bundle
{
// requests
val req_val = Bool('output);
val req_rdy = Bool('input);
val req_vpn = Bits(VPN_BITS, 'output);
val req_val = Bool(OUTPUT);
val req_rdy = Bool(INPUT);
val req_vpn = Bits(VPN_BITS, OUTPUT);
// responses
val resp_val = Bool('input);
val resp_err = Bool('input);
val resp_ppn = Bits(PPN_BITS, 'input);
val resp_perm = Bits(PERM_BITS, 'input);
val resp_val = Bool(INPUT);
val resp_err = Bool(INPUT);
val resp_ppn = Bits(PPN_BITS, INPUT);
val resp_perm = Bits(PERM_BITS, INPUT);
}
// interface between ITLB and fetch stage of pipeline
class ioITLB_CPU(view: List[String] = null) extends Bundle(view)
{
// status bits (from PCR), to check current permission and whether VM is enabled
val status = Bits(17, 'input);
val status = Bits(17, INPUT);
// invalidate all TLB entries
val invalidate = Bool('input);
val invalidate = Bool(INPUT);
// lookup requests
val req_val = Bool('input);
val req_rdy = Bool('output);
val req_asid = Bits(ASID_BITS, 'input);
val req_vpn = UFix(VPN_BITS, 'input);
val req_val = Bool(INPUT);
val req_rdy = Bool(OUTPUT);
val req_asid = Bits(ASID_BITS, INPUT);
val req_vpn = UFix(VPN_BITS, INPUT);
// lookup responses
val resp_miss = Bool('output);
// val resp_val = Bool('output);
val resp_ppn = UFix(PPN_BITS, 'output);
val exception = Bool('output);
val resp_miss = Bool(OUTPUT);
// val resp_val = Bool(OUTPUT);
val resp_ppn = UFix(PPN_BITS, OUTPUT);
val exception = Bool(OUTPUT);
}
class ioITLB extends Bundle

24
rocket/src/main/scala/multiplier.scala
View File

@ -6,20 +6,20 @@ import Constants._;
class ioMultiplier(width: Int) extends Bundle {
// requests
val mul_val = Bool('input);
val mul_kill= Bool('input);
val mul_rdy = Bool('output);
val dw = UFix(1, 'input);
val mul_fn = UFix(2, 'input);
val mul_tag = UFix(CPU_TAG_BITS, 'input);
val in0 = Bits(width, 'input);
val in1 = Bits(width, 'input);
val mul_val = Bool(INPUT);
val mul_kill= Bool(INPUT);
val mul_rdy = Bool(OUTPUT);
val dw = UFix(1, INPUT);
val mul_fn = UFix(2, INPUT);
val mul_tag = UFix(CPU_TAG_BITS, INPUT);
val in0 = Bits(width, INPUT);
val in1 = Bits(width, INPUT);
// responses
val result = Bits(width, 'output);
val result_tag = UFix(CPU_TAG_BITS, 'output);
val result_val = Bool('output);
val result_rdy = Bool('input);
val result = Bits(width, OUTPUT);
val result_tag = UFix(CPU_TAG_BITS, OUTPUT);
val result_val = Bool(OUTPUT);
val result_rdy = Bool(INPUT);
}
class rocketMultiplier extends Component {

116
rocket/src/main/scala/nbdcache.scala
View File

@ -5,11 +5,25 @@ import Node._;
import Constants._;
import scala.math._;
class ReplacementWayGen (width: Int, ways: Int) extends Component {
val io = new Bundle {
val ways_en = Bits(width = width, dir = INPUT)
val way_id = UFix(width = log2up(ways), dir = OUTPUT)
}
}
class RandomReplacementWayGen (width: Int, ways: Int) extends ReplacementWayGen(width, ways) {
val lfsr = Reg(resetVal = UFix(1, width))
when (io.ways_en.orR) { lfsr <== Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) }
//TODO: Actually limit selection based on which ways are available (io.ways_en)
io.way_id := lfsr(log2up(ways)-1,0).toUFix
}
class StoreMaskGen extends Component {
val io = new Bundle {
val typ = Bits(3, 'input)
val addr = Bits(3, 'input)
val wmask = Bits(8, 'output)
val typ = Bits(3, INPUT)
val addr = Bits(3, INPUT)
val wmask = Bits(8, OUTPUT)
}
val word = (io.typ === MT_W) || (io.typ === MT_WU)
@ -24,9 +38,9 @@ class StoreMaskGen extends Component {
class StoreDataGen extends Component {
val io = new Bundle {
val typ = Bits(3, 'input)
val din = Bits(64, 'input)
val dout = Bits(64, 'output)
val typ = Bits(3, INPUT)
val din = Bits(64, INPUT)
val dout = Bits(64, OUTPUT)
}
val word = (io.typ === MT_W) || (io.typ === MT_WU)
@ -42,12 +56,12 @@ class StoreDataGen extends Component {
// this currently requires that CPU_DATA_BITS == 64
class LoadDataGen extends Component {
val io = new Bundle {
val typ = Bits(3, 'input)
val addr = Bits(log2up(MEM_DATA_BITS/8), 'input)
val din = Bits(MEM_DATA_BITS, 'input)
val dout = Bits(64, 'output)
val r_dout = Bits(64, 'output)
val r_dout_subword = Bits(64, 'output)
val typ = Bits(3, INPUT)
val addr = Bits(log2up(MEM_DATA_BITS/8), INPUT)
val din = Bits(MEM_DATA_BITS, INPUT)
val dout = Bits(64, OUTPUT)
val r_dout = Bits(64, OUTPUT)
val r_dout_subword = Bits(64, OUTPUT)
}
val sext = (io.typ === MT_B) || (io.typ === MT_H) ||
@ -135,23 +149,23 @@ class MetaArrayReq extends Bundle {
class MSHR(id: Int) extends Component {
val io = new Bundle {
val req_pri_val = Bool('input)
val req_pri_rdy = Bool('output)
val req_sec_val = Bool('input)
val req_sec_rdy = Bool('output)
val req_ppn = Bits(PPN_BITS, 'input)
val req_idx = Bits(IDX_BITS, 'input)
val req_offset = Bits(OFFSET_BITS, 'input)
val req_cmd = Bits(4, 'input)
val req_type = Bits(3, 'input)
val req_sdq_id = UFix(log2up(NSDQ), 'input)
val req_tag = Bits(DCACHE_TAG_BITS, 'input)
val req_pri_val = Bool(INPUT)
val req_pri_rdy = Bool(OUTPUT)
val req_sec_val = Bool(INPUT)
val req_sec_rdy = Bool(OUTPUT)
val req_ppn = Bits(PPN_BITS, INPUT)
val req_idx = Bits(IDX_BITS, INPUT)
val req_offset = Bits(OFFSET_BITS, INPUT)
val req_cmd = Bits(4, INPUT)
val req_type = Bits(3, INPUT)
val req_sdq_id = UFix(log2up(NSDQ), INPUT)
val req_tag = Bits(DCACHE_TAG_BITS, INPUT)
val idx_match = Bool('output)
val idx = Bits(IDX_BITS, 'output)
val tag = Bits(PPN_BITS, 'output)
val idx_match = Bool(OUTPUT)
val idx = Bits(IDX_BITS, OUTPUT)
val tag = Bits(PPN_BITS, OUTPUT)
val mem_resp_val = Bool('input)
val mem_resp_val = Bool(INPUT)
val mem_req = (new ioDecoupled) { new MemReq() }.flip
val meta_req = (new ioDecoupled) { new MetaArrayReq() }.flip
val replay = (new ioDecoupled) { new Replay() }.flip
@ -228,21 +242,21 @@ class MSHR(id: Int) extends Component {
class MSHRFile extends Component {
val io = new Bundle {
val req_val = Bool('input)
val req_rdy = Bool('output)
val req_ppn = Bits(PPN_BITS, 'input)
val req_idx = Bits(IDX_BITS, 'input)
val req_offset = Bits(OFFSET_BITS, 'input)
val req_cmd = Bits(4, 'input)
val req_type = Bits(3, 'input)
val req_tag = Bits(DCACHE_TAG_BITS, 'input)
val req_sdq_id = UFix(log2up(NSDQ), 'input)
val req_val = Bool(INPUT)
val req_rdy = Bool(OUTPUT)
val req_ppn = Bits(PPN_BITS, INPUT)
val req_idx = Bits(IDX_BITS, INPUT)
val req_offset = Bits(OFFSET_BITS, INPUT)
val req_cmd = Bits(4, INPUT)
val req_type = Bits(3, INPUT)
val req_tag = Bits(DCACHE_TAG_BITS, INPUT)
val req_sdq_id = UFix(log2up(NSDQ), INPUT)
val mem_resp_val = Bool('input)
val mem_resp_tag = Bits(DMEM_TAG_BITS, 'input)
val mem_resp_idx = Bits(IDX_BITS, 'output)
val mem_resp_val = Bool(INPUT)
val mem_resp_tag = Bits(DMEM_TAG_BITS, INPUT)
val mem_resp_idx = Bits(IDX_BITS, OUTPUT)
val fence_rdy = Bool('output)
val fence_rdy = Bool(OUTPUT)
val mem_req = (new ioDecoupled) { new MemReq() }.flip()
val meta_req = (new ioDecoupled) { new MetaArrayReq() }.flip()
@ -311,11 +325,11 @@ class MSHRFile extends Component {
class ReplayUnit extends Component {
val io = new Bundle {
val sdq_enq = (new ioDecoupled) { Bits(width = CPU_DATA_BITS) }
val sdq_id = UFix(log2up(NSDQ), 'output)
val sdq_id = UFix(log2up(NSDQ), OUTPUT)
val replay = (new ioDecoupled) { new Replay() }
val data_req = (new ioDecoupled) { new DataReq() }.flip()
val cpu_resp_val = Bool('output)
val cpu_resp_tag = Bits(DCACHE_TAG_BITS, 'output)
val cpu_resp_val = Bool(OUTPUT)
val cpu_resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT)
}
val sdq_val = Reg(resetVal = UFix(0, NSDQ))
@ -370,10 +384,10 @@ class WritebackUnit extends Component {
val io = new Bundle {
val req = (new ioDecoupled) { new WritebackReq() }
val data_req = (new ioDecoupled) { new DataArrayReq() }.flip()
val data_resp = Bits(MEM_DATA_BITS, 'input)
val data_resp = Bits(MEM_DATA_BITS, INPUT)
val refill_req = (new ioDecoupled) { new MemReq() }
val mem_req = (new ioDecoupled) { new MemReq() }.flip()
val mem_req_data = Bits(MEM_DATA_BITS, 'output)
val mem_req_data = Bits(MEM_DATA_BITS, OUTPUT)
}
val wbq = (new queueSimplePF(REFILL_CYCLES)) { Bits(width = MEM_DATA_BITS) }
@ -483,7 +497,7 @@ class MetaDataArray(lines: Int) extends Component {
class DataArray(lines: Int) extends Component {
val io = new Bundle {
val req = (new ioDecoupled) { new DataArrayReq() }
val resp = Bits(width = MEM_DATA_BITS, dir = 'output)
val resp = Bits(width = MEM_DATA_BITS, dir = OUTPUT)
}
val wmask = FillInterleaved(8, io.req.bits.wmask)
@ -499,11 +513,11 @@ class DataArray(lines: Int) extends Component {
class AMOALU extends Component {
val io = new Bundle {
val cmd = Bits(4, 'input)
val typ = Bits(3, 'input)
val lhs = UFix(64, 'input)
val rhs = UFix(64, 'input)
val out = UFix(64, 'output)
val cmd = Bits(4, INPUT)
val typ = Bits(3, INPUT)
val lhs = UFix(64, INPUT)
val rhs = UFix(64, INPUT)
val out = UFix(64, OUTPUT)
}
val sgned = (io.cmd === M_XA_MIN) || (io.cmd === M_XA_MAX)

2
rocket/src/main/scala/ptw.scala
View File

@ -53,7 +53,7 @@ class ioPTW extends Bundle
val itlb = new ioTLB_PTW().flip();
val dtlb = new ioTLB_PTW().flip();
val dmem = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "req_ppn", "req_idx", "resp_data", "resp_val", "resp_nack")).flip();
val ptbr = UFix(PADDR_BITS, 'input);
val ptbr = UFix(PADDR_BITS, INPUT);
}
class rocketPTW extends Component

50
rocket/src/main/scala/queues.scala
View File

@ -7,14 +7,14 @@ import scala.math._;
class ioQueueCtrl(addr_sz: Int) extends Bundle()
{
val q_reset = Bool('input);
val enq_val = Bool('input);
val enq_rdy = Bool('output);
val deq_val = Bool('output);
val deq_rdy = Bool('input);
val wen = Bool('output);
val waddr = UFix(addr_sz, 'output);
val raddr = UFix(addr_sz, 'output);
val q_reset = Bool(INPUT);
val enq_val = Bool(INPUT);
val enq_rdy = Bool(OUTPUT);
val deq_val = Bool(OUTPUT);
val deq_rdy = Bool(INPUT);
val wen = Bool(OUTPUT);
val waddr = UFix(addr_sz, OUTPUT);
val raddr = UFix(addr_sz, OUTPUT);
}
class queueCtrl(entries: Int) extends Component
@ -83,7 +83,7 @@ class queueCtrl(entries: Int) extends Component
class ioQueueSimplePF[T <: Data]()(data: => T) extends Bundle
{
val q_reset = Bool('input);
val q_reset = Bool(INPUT);
val enq = new ioDecoupled()(data)
val deq = new ioDecoupled()(data).flip
}
@ -105,14 +105,14 @@ class queueSimplePF[T <: Data](entries: Int)(data: => T) extends Component
// class IOqueueCtrlFlow extends IOqueueCtrl
class ioQueueCtrlFlow(addr_sz: Int) extends Bundle() /* IOqueueCtrl */
{
val enq_val = Bool('input);
val enq_rdy = Bool('output);
val deq_val = Bool('output);
val deq_rdy = Bool('input);
val wen = Bool('output);
val waddr = UFix(addr_sz, 'output);
val raddr = UFix(addr_sz, 'output);
val flowthru = Bool('output);
val enq_val = Bool(INPUT);
val enq_rdy = Bool(OUTPUT);
val deq_val = Bool(OUTPUT);
val deq_rdy = Bool(INPUT);
val wen = Bool(OUTPUT);
val waddr = UFix(addr_sz, OUTPUT);
val raddr = UFix(addr_sz, OUTPUT);
val flowthru = Bool(OUTPUT);
}
class queueCtrlFlow(entries: Int) extends Component
@ -176,12 +176,12 @@ class queueCtrlFlow(entries: Int) extends Component
class ioQueueDpathFlow[T <: Data](addr_sz: Int)(data: => T) extends Bundle()
{
val wen = Bool('input);
val flowthru = Bool('input);
val wen = Bool(INPUT);
val flowthru = Bool(INPUT);
val deq_bits = data.asOutput;
val enq_bits = data.asInput;
val waddr = UFix(addr_sz, 'input);
val raddr = UFix(addr_sz, 'input);
val waddr = UFix(addr_sz, INPUT);
val raddr = UFix(addr_sz, INPUT);
}
class queueDpathFlow[T <: Data](entries: Int)(data: => T) extends Component
@ -195,11 +195,11 @@ class queueDpathFlow[T <: Data](entries: Int)(data: => T) extends Component
class ioQueueFlowPF[T <: Data](data: => T) extends Bundle()
{
val enq_val = Bool('input);
val enq_rdy = Bool('output);
val enq_val = Bool(INPUT);
val enq_rdy = Bool(OUTPUT);
val enq_bits = data.asInput;
val deq_val = Bool('output);
val deq_rdy = Bool('input);
val deq_val = Bool(OUTPUT);
val deq_rdy = Bool(INPUT);
val deq_bits = data.asOutput;
}

18
rocket/src/main/scala/util.scala
View File

@ -35,9 +35,9 @@ object Reverse
class Mux1H(n: Int, w: Int) extends Component
{
val io = new Bundle {
val sel = Vec(n) { Bool(dir = 'input) }
val in = Vec(n) { Bits(width = w, dir = 'input) }
val out = Bits(width = w, dir = 'output)
val sel = Vec(n) { Bool(dir = INPUT) }
val in = Vec(n) { Bits(width = w, dir = INPUT) }
val out = Bits(width = w, dir = OUTPUT)
}
if (n > 1) {
@ -52,8 +52,8 @@ class Mux1H(n: Int, w: Int) extends Component
class ioDecoupled[T <: Data]()(data: => T) extends Bundle
{
val valid = Bool('input)
val ready = Bool('output)
val valid = Bool(INPUT)
val ready = Bool(OUTPUT)
val bits = data.asInput
}
@ -84,8 +84,8 @@ class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
class ioPriorityDecoder(in_width: Int, out_width: Int) extends Bundle
{
val in = UFix(in_width, 'input);
val out = Bits(out_width, 'output);
val in = UFix(in_width, INPUT);
val out = Bits(out_width, OUTPUT);
}
class priorityDecoder(width: Int) extends Component
@ -106,8 +106,8 @@ class priorityDecoder(width: Int) extends Component
class ioPriorityEncoder(in_width: Int, out_width: Int) extends Bundle
{
val in = Bits(in_width, 'input);
val out = UFix(out_width, 'output);
val in = Bits(in_width, INPUT);
val out = UFix(out_width, OUTPUT);
}
class priorityEncoder(width: Int) extends Component