riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

new chisel version jar and find and replace INPUT and OUTPUT

Browse Source
This commit is contained in:
Henry Cook committed 2012-01-18 14:39:57 -08:00
1 parent e4cf6391d7
commit 1d76255dc1
18 files changed
+372 -358
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

rocket/src/main/scala/ptw.scala
+1 -1
View File
@@ -53,7 +53,7 @@ class ioPTW extends Bundle
val itlb = new ioTLB_PTW().flip();
val dtlb = new ioTLB_PTW().flip();
val dmem = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "req_ppn", "req_idx", "resp_data", "resp_val", "resp_nack")).flip();
val ptbr = UFix(PADDR_BITS, 'input);
val ptbr = UFix(PADDR_BITS, INPUT);
}
class rocketPTW extends Component