riscv/rocket-chip
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new chisel version jar and find and replace INPUT and OUTPUT

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This commit is contained in:
Henry Cook
2012-01-18 10:28:48 -08:00
parent e4cf6391d7
commit 1d76255dc1
18 changed files with 372 additions and 358 deletions
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26
rocket/src/main/scala/dpath.scala
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@ -7,21 +7,21 @@ import Instructions._
class ioDpathDmem extends Bundle()
{
val req_addr = UFix(VADDR_BITS, 'output);
val req_tag = UFix(CPU_TAG_BITS, 'output);
val req_data = Bits(64, 'output);
val resp_val = Bool('input);
val resp_miss = Bool('input);
val resp_replay = Bool('input);
val resp_tag = Bits(CPU_TAG_BITS, 'input);
val resp_data = Bits(64, 'input);
val resp_data_subword = Bits(64, 'input);
val req_addr = UFix(VADDR_BITS, OUTPUT);
val req_tag = UFix(CPU_TAG_BITS, OUTPUT);
val req_data = Bits(64, OUTPUT);
val resp_val = Bool(INPUT);
val resp_miss = Bool(INPUT);
val resp_replay = Bool(INPUT);
val resp_tag = Bits(CPU_TAG_BITS, INPUT);
val resp_data = Bits(64, INPUT);
val resp_data_subword = Bits(64, INPUT);
}
class ioDpathImem extends Bundle()
{
val req_addr = UFix(VADDR_BITS, 'output);
val resp_data = Bits(32, 'input);
val req_addr = UFix(VADDR_BITS, OUTPUT);
val resp_data = Bits(32, INPUT);
}
class ioDpathAll extends Bundle()
@ -32,8 +32,8 @@ class ioDpathAll extends Bundle()
val debug = new ioDebug();
val dmem = new ioDpathDmem();
val imem = new ioDpathImem();
val ptbr_wen = Bool('output);
val ptbr = UFix(PADDR_BITS, 'output);
val ptbr_wen = Bool(OUTPUT);
val ptbr = UFix(PADDR_BITS, OUTPUT);
}
class rocketDpath extends Component