riscv/rocket-chip
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new chisel version jar and find and replace INPUT and OUTPUT

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This commit is contained in:
Henry Cook
2012-01-18 10:28:48 -08:00
parent e4cf6391d7
commit 1d76255dc1
18 changed files with 372 additions and 358 deletions
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14
rocket/src/main/scala/cpu.scala
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@ -6,21 +6,21 @@ import Constants._;
class ioDebug(view: List[String] = null) extends Bundle(view)
{
val error_mode = Bool('output);
val error_mode = Bool(OUTPUT);
}
class ioHost(view: List[String] = null) extends Bundle(view)
{
val from_wen = Bool('input);
val from = Bits(64, 'input);
val to = Bits(64, 'output);
val from_wen = Bool(INPUT);
val from = Bits(64, INPUT);
val to = Bits(64, OUTPUT);
}
class ioConsole(view: List[String] = null) extends Bundle(view)
{
val rdy = Bool('input);
val valid = Bool('output);
val bits = Bits(8, 'output);
val rdy = Bool(INPUT);
val valid = Bool(OUTPUT);
val bits = Bits(8, OUTPUT);
}
class ioRocket extends Bundle()