diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala
index 61f35e0c..8b55c39f 100644
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@@ -207,11 +207,6 @@ object Constants
   val DTLB_ENTRIES = 8;
   val ITLB_ENTRIES = 8;
   
-  // physical memory size (# 8K pages)
-  // if you change this value, make sure to also change MEMORY_SIZE variable in memif.h
-  val MEMSIZE_PAGES = 0x8000; // 256 megs
-  val MEMSIZE_BYTES = MEMSIZE_PAGES*8192;
-  
   val START_ADDR = 0x2000;
   
   val HAVE_RVC = false
diff --git a/rocket/src/main/scala/dtlb.scala b/rocket/src/main/scala/dtlb.scala
index f7c8f17b..6c0af2a0 100644
--- a/rocket/src/main/scala/dtlb.scala
+++ b/rocket/src/main/scala/dtlb.scala
@@ -141,9 +141,6 @@ class rocketDTLB(entries: Int) extends Component
     }
   }
 
-  // exception check
-  val outofrange = !tlb_miss && (io.cpu_resp.ppn > UFix(MEMSIZE_PAGES, PPN_BITS));
-
    val access_fault_ld =
     tlb_hit && (req_load || req_amo) &&
     ((status_s && !sr_array(tag_hit_addr).toBool) ||