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tilelink2 SourceShrinker: handle degenerate cases for free

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This commit is contained in:
Wesley W. Terpstra 2016-11-22 22:01:43 -08:00
parent 1e7d597fd3
commit 1d3cad3671
1 changed files with 30 additions and 23 deletions
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53
src/main/scala/uncore/tilelink2/SourceShrinker.scala
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@ -9,6 +9,8 @@ import scala.math.{min,max}
class TLSourceShrinker(maxInFlight: Int) extends LazyModule class TLSourceShrinker(maxInFlight: Int) extends LazyModule
{ {
require (maxInFlight > 0)
private val client = TLClientParameters(sourceId = IdRange(0, maxInFlight)) private val client = TLClientParameters(sourceId = IdRange(0, maxInFlight))
val node = TLAdapterNode( val node = TLAdapterNode(
// We erase all client information since we crush the source Ids // We erase all client information since we crush the source Ids
@ -37,34 +39,39 @@ class TLSourceShrinker(maxInFlight: Int) extends LazyModule
in.c.ready := Bool(true) in.c.ready := Bool(true)
in.e.ready := Bool(true) in.e.ready := Bool(true)
// State tracking if (maxInFlight >= edgeIn.client.endSourceId) {
val sourceIdMap = Mem(maxInFlight, in.a.bits.source) out.a <> in.a
val allocated = RegInit(UInt(0, width = maxInFlight)) in.d <> out.d
val nextFreeOH = ~(leftOR(~allocated) << 1) & ~allocated } else {
val nextFree = OHToUInt(nextFreeOH) // State tracking
val full = allocated.andR() val sourceIdMap = Mem(maxInFlight, in.a.bits.source)
val allocated = RegInit(UInt(0, width = maxInFlight))
val nextFreeOH = ~(leftOR(~allocated) << 1) & ~allocated
val nextFree = OHToUInt(nextFreeOH)
val full = allocated.andR()
val a_first = edgeIn.first(in.a) val a_first = edgeIn.first(in.a)
val d_last = edgeIn.last(in.d) val d_last = edgeIn.last(in.d)
val block = a_first && full val block = a_first && full
in.a.ready := out.a.ready && !block in.a.ready := out.a.ready && !block
out.a.valid := in.a.valid && !block out.a.valid := in.a.valid && !block
out.a.bits := in.a.bits out.a.bits := in.a.bits
out.a.bits.source := holdUnless(nextFree, a_first) out.a.bits.source := holdUnless(nextFree, a_first)
in.d <> out.d in.d <> out.d
in.d.bits.source := sourceIdMap(out.d.bits.source) in.d.bits.source := sourceIdMap(out.d.bits.source)
when (a_first && in.a.fire()) { when (a_first && in.a.fire()) {
sourceIdMap(nextFree) := in.a.bits.source sourceIdMap(nextFree) := in.a.bits.source
}
val alloc = a_first && in.a.fire()
val free = d_last && in.d.fire()
val alloc_id = Mux(alloc, nextFreeOH, UInt(0))
val free_id = Mux(free, UIntToOH(out.d.bits.source), UInt(0))
allocated := (allocated | alloc_id) & ~free_id
} }
val alloc = a_first && in.a.fire()
val free = d_last && in.d.fire()
val alloc_id = Mux(alloc, nextFreeOH, UInt(0))
val free_id = Mux(free, UIntToOH(out.d.bits.source), UInt(0))
allocated := (allocated | alloc_id) & ~free_id
} }
} }