From 1d2f4f8437baf16051d74d35ec4d65b93c9ce40e Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 21 Sep 2013 06:32:40 -0700 Subject: [PATCH] New ISA encoding, AUIPC semantics --- rocket/src/main/scala/consts.scala | 5 +- rocket/src/main/scala/ctrl.scala | 20 +- rocket/src/main/scala/dpath.scala | 46 +-- rocket/src/main/scala/fpu.scala | 10 +- rocket/src/main/scala/instructions.scala | 366 +++++++++++------------ 5 files changed, 224 insertions(+), 223 deletions(-) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 3309bab0..b8970e9e 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -22,8 +22,9 @@ trait ScalarOpConstants { val A1_X = Bits("b??", 2) val A1_RS1 = UInt(0, 2) - val A1_PC = UInt(1, 2) - val A1_ZERO = UInt(2, 2) + val A1_ZERO = UInt(1, 2) + val A1_PC = UInt(2, 2) + val A1_PCHI = UInt(3, 2) val IMM_X = Bits("b???", 3) val IMM_S = UInt(0, 3); diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 2a4da7af..60fb8dd7 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -100,7 +100,7 @@ object XDecode extends DecodeConstants JAL-> List(Y, N,N,BR_J, N,N,N,A2_FOUR,A1_PC, IMM_UJ,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), JALR-> List(Y, N,N,BR_N, Y,N,Y,A2_FOUR,A1_PC, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), - AUIPC-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), + AUIPC-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_PCHI,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LB-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), LH-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N), @@ -189,7 +189,7 @@ object XDecode extends DecodeConstants CLEARPCR-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_ZERO,IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.C,N,N,N,Y,N,N,N), ERET-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,Y,N,Y,N,N,N), FENCE-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,Y,N), - FENCE_I-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,Y,N,N,N,Y,Y,N), + FENCE_I-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,Y,N,N,N,Y,N,N), MFPCR-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WB_X, PCR.F,N,N,N,Y,N,N,N), MTPCR-> List(Y, N,N,BR_N, N,Y,N,A2_RS2, A1_ZERO,IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.T,N,N,N,Y,N,N,N), RDTIME-> List(Y, N,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_XPR,FN_X, N,M_X, MT_X, N,N,Y,WB_TSC,PCR.N,N,N,N,N,N,N,N), @@ -395,11 +395,11 @@ class Control(implicit conf: RocketConfiguration) extends Module val ctrl_killx = Bool() val ctrl_killm = Bool() - val id_raddr3 = io.dpath.inst(16,12) - val id_raddr2 = io.dpath.inst(21,17) - val id_raddr1 = io.dpath.inst(26,22) - val id_waddr = io.dpath.inst(31,27) - val id_load_use = Bool(); + val id_raddr3 = io.dpath.inst(31,27) + val id_raddr2 = io.dpath.inst(24,20) + val id_raddr1 = io.dpath.inst(19,15) + val id_waddr = io.dpath.inst(11,7) + val id_load_use = Bool() val id_reg_fence = Reg(init=Bool(false)) val sr = io.dpath.status @@ -416,14 +416,14 @@ class Control(implicit conf: RocketConfiguration) extends Module id_raddr1 != PCR.SUP0 && id_raddr1 != PCR.SUP1 && id_raddr1 != PCR.EPC // stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE) - val id_amo_aq = io.dpath.inst(16) - val id_amo_rl = io.dpath.inst(15) + val id_amo_aq = io.dpath.inst(26) + val id_amo_rl = io.dpath.inst(25) val id_fence_next = id_fence || id_amo && id_amo_rl val id_rocc_busy = io.rocc.busy || ex_reg_rocc_val || mem_reg_rocc_val || wb_reg_rocc_val val id_fence_ok = io.dmem.ordered && !ex_reg_mem_val && (Bool(conf.rocc.isEmpty) || !id_rocc_busy) id_reg_fence := id_fence_next || id_reg_fence && !id_fence_ok - val id_do_fence = id_amo && id_amo_aq || id_reg_fence && (id_mem_val || id_rocc_val) || id_pcr_flush + val id_do_fence = id_amo && id_amo_aq || id_fence_i || id_reg_fence && (id_mem_val || id_rocc_val) || id_pcr_flush val (id_xcpt, id_cause) = checkExceptions(List( (id_interrupt, id_interrupt_cause), diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index 21dd1c08..23c54a4a 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -59,8 +59,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Module def readRF(a: UInt) = regfile_(~a) def writeRF(a: UInt, d: Bits) = regfile_(~a) := d - val id_raddr1 = id_inst(26,22).toUInt; - val id_raddr2 = id_inst(21,17).toUInt; + val id_raddr1 = id_inst(19,15).toUInt; + val id_raddr2 = id_inst(24,20).toUInt; // bypass muxes val id_rs1_zero = id_raddr1 === UInt(0) @@ -79,18 +79,18 @@ class Datapath(implicit conf: RocketConfiguration) extends Module // immediate generation def imm(sel: Bits, inst: Bits) = { - val sign = inst(10).toSInt - val b30_20 = Mux(sel === IMM_U, inst(21,11).toSInt, sign) - val b19_12 = Mux(sel != IMM_U && sel != IMM_UJ, sign, - Cat(inst(9,7), inst(26,22)).toSInt) + val sign = inst(31).toSInt + val b30_20 = Mux(sel === IMM_U, inst(30,20).toSInt, sign) + val b19_12 = Mux(sel != IMM_U && sel != IMM_UJ, sign, inst(19,12).toSInt) val b11 = Mux(sel === IMM_U, SInt(0), - Mux(sel === IMM_SB || sel === IMM_UJ, inst(11).toSInt, sign)) - val b10_6 = Mux(sel === IMM_S || sel === IMM_SB, inst(31,27), - Mux(sel === IMM_U, Bits(0), inst(21,17))) - val b5_1 = Mux(sel === IMM_U, Bits(0), inst(16,12)) - val b0 = Mux(sel === IMM_I || sel === IMM_S, inst(11), Bits(0)) + Mux(sel === IMM_UJ, inst(20).toSInt, + Mux(sel === IMM_SB, inst(7).toSInt, sign))) + val b10_5 = Mux(sel === IMM_U, Bits(0), inst(30,25)) + val b4_1 = Mux(sel === IMM_U, Bits(0), + Mux(sel === IMM_S || sel === IMM_SB, inst(11,8), inst(24,21))) + val b0 = Mux(sel === IMM_S, inst(7), Mux(sel === IMM_I, inst(20), Bits(0))) - Cat(sign, b30_20, b19_12, b11, b10_6, b5_1, b0).toSInt + Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).toSInt } io.ctrl.inst := id_inst @@ -125,8 +125,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Module } } - val ex_raddr1 = ex_reg_inst(26,22) - val ex_raddr2 = ex_reg_inst(21,17) + val ex_raddr1 = ex_reg_inst(19,15) + val ex_raddr2 = ex_reg_inst(24,20) val dmem_resp_data = if (conf.fastLoadByte) io.dmem.resp.bits.data_subword else io.dmem.resp.bits.data val ex_rs1 = @@ -134,7 +134,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UInt(2), wb_reg_wdata, Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UInt(1), mem_reg_wdata, Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UInt(0), Bits(0), - Mux(ex_reg_sel_alu1 === A1_ZERO, Bits(0), + Mux(AVec(A1_ZERO, A1_PCHI) contains ex_reg_sel_alu1, Bits(0), Cat(ex_reg_rs1_msb, ex_reg_rs1_lsb)))))) val ex_rs2 = Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UInt(3) && Bool(conf.fastLoadWord), dmem_resp_data, @@ -144,7 +144,9 @@ class Datapath(implicit conf: RocketConfiguration) extends Module Cat(ex_reg_rs2_msb, ex_reg_rs2_lsb))))) val ex_imm = imm(ex_reg_sel_imm, ex_reg_inst) - val ex_op1 = Mux(ex_reg_sel_alu1 === A1_PC, ex_reg_pc.toSInt, ex_rs1) + val ex_op1_hi = Mux(AVec(A1_PC, A1_PCHI) contains ex_reg_sel_alu1, ex_reg_pc >> 12, ex_rs1 >> 12).toSInt + val ex_op1_lo = Mux(ex_reg_sel_alu1 === A1_PC, ex_reg_pc(11,0), ex_rs1(11,0)).toSInt + val ex_op1 = Cat(ex_op1_hi, ex_op1_lo) val ex_op2 = Mux(ex_reg_sel_alu2 === A2_RS2, ex_rs2.toSInt, Mux(ex_reg_sel_alu2 === A2_IMM, ex_imm, Mux(ex_reg_sel_alu2 === A2_ZERO, SInt(0), @@ -170,7 +172,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module io.ctrl.div_mul_rdy := div.io.req.ready io.fpu.fromint_data := ex_rs1 - io.ctrl.ex_waddr := ex_reg_inst(31,27) + io.ctrl.ex_waddr := ex_reg_inst(11,7) def vaSign(a0: UInt, ea: Bits) = { // efficient means to compress 64-bit VA into VADDR_BITS+1 bits @@ -207,7 +209,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module io.ptw.status := pcr.io.status // branch resolution logic - io.ctrl.jalr_eq := ex_rs1 === id_pc.toSInt && ex_reg_inst(21,10) === UInt(0) + io.ctrl.jalr_eq := ex_rs1 === id_pc.toSInt && ex_reg_inst(31,20) === UInt(0) io.ctrl.ex_br_taken := Mux(io.ctrl.ex_br_type === BR_EQ, ex_rs1 === ex_rs2, Mux(io.ctrl.ex_br_type === BR_NE, ex_rs1 != ex_rs2, @@ -238,7 +240,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module } // for load/use hazard detection (load byte/halfword) - io.ctrl.mem_waddr := mem_reg_inst(31,27) + io.ctrl.mem_waddr := mem_reg_inst(11,7) // writeback arbitration val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool @@ -302,7 +304,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module io.ctrl.fp_sboard_clra := dmem_resp_waddr // processor control regfile write - pcr.io.rw.addr := wb_reg_inst(26,22).toUInt + pcr.io.rw.addr := wb_reg_inst(19,15).toUInt pcr.io.rw.cmd := io.ctrl.pcr pcr.io.rw.wdata := wb_reg_wdata @@ -320,7 +322,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", tsc_reg(32,0), io.ctrl.wb_valid, wb_reg_pc, Mux(wb_wen, wb_reg_waddr, UInt(0)), wb_wdata, - wb_reg_inst(26,22), Reg(next=Reg(next=ex_rs1)), - wb_reg_inst(21,17), Reg(next=Reg(next=ex_rs2)), + wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs1)), + wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs2)), wb_reg_inst, wb_reg_inst) } diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index a83724af..c272999a 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -479,10 +479,10 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module val regfile = Mem(Bits(width = 65), 32) when (load_wb) { regfile(load_wb_tag) := load_wb_data_recoded } - val ex_rs1 = regfile(ex_reg_inst(26,22)) - val ex_rs2 = regfile(ex_reg_inst(21,17)) - val ex_rs3 = regfile(ex_reg_inst(16,12)) - val ex_rm = Mux(ex_reg_inst(11,9) === Bits(7), fsr_rm, ex_reg_inst(11,9)) + val ex_rs1 = regfile(ex_reg_inst(19,15)) + val ex_rs2 = regfile(ex_reg_inst(24,20)) + val ex_rs3 = regfile(ex_reg_inst(31,27)) + val ex_rm = Mux(ex_reg_inst(14,12) === Bits(7), fsr_rm, ex_reg_inst(14,12)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := ex_reg_valid && ctrl.toint @@ -552,7 +552,7 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module val (write_port_busy, mem_winfo) = (Reg(Bool()), Reg(Bits())) when (ex_reg_valid) { write_port_busy := mem_wen && (memLatencyMask & latencyMask(ctrl, 1)).orR || (wen & latencyMask(ctrl, 0)).orR - mem_winfo := Cat(pipeid(ctrl), ex_reg_inst(31,27)) + mem_winfo := Cat(pipeid(ctrl), ex_reg_inst(11,7)) } for (i <- 0 until maxLatency-2) { diff --git a/rocket/src/main/scala/instructions.scala b/rocket/src/main/scala/instructions.scala index 9273d1c2..91349e66 100644 --- a/rocket/src/main/scala/instructions.scala +++ b/rocket/src/main/scala/instructions.scala @@ -6,189 +6,187 @@ import Node._ object Instructions { /* Automatically generated by parse-opcodes */ - def JAL = Bits("b?????????????????????????1100111") - def JALR = Bits("b??????????????????????0001101111") - def BEQ = Bits("b??????????????????????0001100011") - def BNE = Bits("b??????????????????????0011100011") - def BLT = Bits("b??????????????????????1001100011") - def BGE = Bits("b??????????????????????1011100011") - def BLTU = Bits("b??????????????????????1101100011") - def BGEU = Bits("b??????????????????????1111100011") - def LUI = Bits("b?????????????????????????0110111") - def AUIPC = Bits("b?????????????????????????0010111") - def ADDI = Bits("b??????????????????????0000010011") - def SLLI = Bits("b??????????00000??????00010010011") - def SLTI = Bits("b??????????????????????0100010011") - def SLTIU = Bits("b??????????????????????0110010011") - def XORI = Bits("b??????????????????????1000010011") - def SRLI = Bits("b??????????00000??????01010010011") - def SRAI = Bits("b??????????00000??????11010010011") - def ORI = Bits("b??????????????????????1100010011") - def ANDI = Bits("b??????????????????????1110010011") - def ADD = Bits("b???????????????00000000000110011") - def SUB = Bits("b???????????????10000000000110011") - def SLL = Bits("b???????????????00000000010110011") - def SLT = Bits("b???????????????00000000100110011") - def SLTU = Bits("b???????????????00000000110110011") - def XOR = Bits("b???????????????00000001000110011") - def SRL = Bits("b???????????????00000001010110011") - def SRA = Bits("b???????????????10000001010110011") - def OR = Bits("b???????????????00000001100110011") - def AND = Bits("b???????????????00000001110110011") - def MUL = Bits("b???????????????00000010000110011") - def MULH = Bits("b???????????????00000010010110011") - def MULHSU = Bits("b???????????????00000010100110011") - def MULHU = Bits("b???????????????00000010110110011") - def DIV = Bits("b???????????????00000011000110011") - def DIVU = Bits("b???????????????00000011010110011") - def REM = Bits("b???????????????00000011100110011") - def REMU = Bits("b???????????????00000011110110011") - def ADDIW = Bits("b??????????????????????0000011011") - def SLLIW = Bits("b??????????000000?????00010011011") - def SRLIW = Bits("b??????????000000?????01010011011") - def SRAIW = Bits("b??????????000000?????11010011011") - def ADDW = Bits("b???????????????00000000000111011") - def SUBW = Bits("b???????????????10000000000111011") - def SLLW = Bits("b???????????????00000000010111011") - def SRLW = Bits("b???????????????00000001010111011") - def SRAW = Bits("b???????????????10000001010111011") - def MULW = Bits("b???????????????00000010000111011") - def DIVW = Bits("b???????????????00000011000111011") - def DIVUW = Bits("b???????????????00000011010111011") - def REMW = Bits("b???????????????00000011100111011") - def REMUW = Bits("b???????????????00000011110111011") - def LB = Bits("b??????????????????????0000000011") - def LH = Bits("b??????????????????????0010000011") - def LW = Bits("b??????????????????????0100000011") - def LD = Bits("b??????????????????????0110000011") - def LBU = Bits("b??????????????????????1000000011") - def LHU = Bits("b??????????????????????1010000011") - def LWU = Bits("b??????????????????????1100000011") - def SB = Bits("b??????????????????????0000100011") - def SH = Bits("b??????????????????????0010100011") - def SW = Bits("b??????????????????????0100100011") - def SD = Bits("b??????????????????????0110100011") - def AMOADD_W = Bits("b?????????????????000000100101011") - def AMOXOR_W = Bits("b?????????????????001000100101011") - def AMOOR_W = Bits("b?????????????????010000100101011") - def AMOAND_W = Bits("b?????????????????011000100101011") - def AMOMIN_W = Bits("b?????????????????100000100101011") - def AMOMAX_W = Bits("b?????????????????101000100101011") - def AMOMINU_W = Bits("b?????????????????110000100101011") - def AMOMAXU_W = Bits("b?????????????????111000100101011") - def AMOSWAP_W = Bits("b?????????????????000010100101011") - def LR_W = Bits("b??????????00000??000100100101011") - def SC_W = Bits("b?????????????????000110100101011") - def AMOADD_D = Bits("b?????????????????000000110101011") - def AMOXOR_D = Bits("b?????????????????001000110101011") - def AMOOR_D = Bits("b?????????????????010000110101011") - def AMOAND_D = Bits("b?????????????????011000110101011") - def AMOMIN_D = Bits("b?????????????????100000110101011") - def AMOMAX_D = Bits("b?????????????????101000110101011") - def AMOMINU_D = Bits("b?????????????????110000110101011") - def AMOMAXU_D = Bits("b?????????????????111000110101011") - def AMOSWAP_D = Bits("b?????????????????000010110101011") - def LR_D = Bits("b??????????00000??000100110101011") - def SC_D = Bits("b?????????????????000110110101011") - def FENCE = Bits("b???????????????????????000101111") - def FENCE_I = Bits("b???????????????????????010101111") - def FENCE_V_L = Bits("b???????????????????????100101111") - def FENCE_V_G = Bits("b???????????????????????110101111") - def SYSCALL = Bits("b00000000000000000000000001110111") - def BREAK = Bits("b00000000000000000000000011110111") - def RDCYCLE = Bits("b?????000000000000000001001110111") - def RDTIME = Bits("b?????000000000000000011001110111") - def RDINSTRET = Bits("b?????000000000000000101001110111") - def MTPCR = Bits("b???????????????00000000001110011") - def MFPCR = Bits("b??????????0000000000000011110011") - def SETPCR = Bits("b??????????????????????0101110011") - def CLEARPCR = Bits("b??????????????????????0111110011") - def ERET = Bits("b00000000000000000000001001110011") - def FADD_S = Bits("b???????????????00000???001010011") - def FSUB_S = Bits("b???????????????00001???001010011") - def FMUL_S = Bits("b???????????????00010???001010011") - def FDIV_S = Bits("b???????????????00011???001010011") - def FSQRT_S = Bits("b??????????0000000100???001010011") - def FSGNJ_S = Bits("b???????????????00101000001010011") - def FSGNJN_S = Bits("b???????????????00110000001010011") - def FSGNJX_S = Bits("b???????????????00111000001010011") - def FADD_D = Bits("b???????????????00000???011010011") - def FSUB_D = Bits("b???????????????00001???011010011") - def FMUL_D = Bits("b???????????????00010???011010011") - def FDIV_D = Bits("b???????????????00011???011010011") - def FSQRT_D = Bits("b??????????0000000100???011010011") - def FSGNJ_D = Bits("b???????????????00101000011010011") - def FSGNJN_D = Bits("b???????????????00110000011010011") - def FSGNJX_D = Bits("b???????????????00111000011010011") - def FCVT_L_S = Bits("b??????????0000001000???001010011") - def FCVT_LU_S = Bits("b??????????0000001001???001010011") - def FCVT_W_S = Bits("b??????????0000001010???001010011") - def FCVT_WU_S = Bits("b??????????0000001011???001010011") - def FCVT_L_D = Bits("b??????????0000001000???011010011") - def FCVT_LU_D = Bits("b??????????0000001001???011010011") - def FCVT_W_D = Bits("b??????????0000001010???011010011") - def FCVT_WU_D = Bits("b??????????0000001011???011010011") - def FCVT_S_L = Bits("b??????????0000001100???001010011") - def FCVT_S_LU = Bits("b??????????0000001101???001010011") - def FCVT_S_W = Bits("b??????????0000001110???001010011") - def FCVT_S_WU = Bits("b??????????0000001111???001010011") - def FCVT_D_L = Bits("b??????????0000001100???011010011") - def FCVT_D_LU = Bits("b??????????0000001101???011010011") - def FCVT_D_W = Bits("b??????????0000001110???011010011") - def FCVT_D_WU = Bits("b??????????0000001111???011010011") - def FCVT_S_D = Bits("b??????????0000010001???001010011") - def FCVT_D_S = Bits("b??????????0000010000???011010011") - def FEQ_S = Bits("b???????????????10101000001010011") - def FLT_S = Bits("b???????????????10110000001010011") - def FLE_S = Bits("b???????????????10111000001010011") - def FEQ_D = Bits("b???????????????10101000011010011") - def FLT_D = Bits("b???????????????10110000011010011") - def FLE_D = Bits("b???????????????10111000011010011") - def FMIN_S = Bits("b???????????????11000000001010011") - def FMAX_S = Bits("b???????????????11001000001010011") - def FMIN_D = Bits("b???????????????11000000011010011") - def FMAX_D = Bits("b???????????????11001000011010011") - def FMV_X_S = Bits("b??????????0000011100000001010011") - def FMV_X_D = Bits("b??????????0000011100000011010011") - def FRSR = Bits("b?????000000000011101000001010011") - def FMV_S_X = Bits("b??????????0000011110000001010011") - def FMV_D_X = Bits("b??????????0000011110000011010011") - def FSSR = Bits("b??????????0000011111000001010011") - def FLW = Bits("b??????????????????????0100000111") - def FLD = Bits("b??????????????????????0110000111") - def FSW = Bits("b??????????????????????0100100111") - def FSD = Bits("b??????????????????????0110100111") - def FMADD_S = Bits("b???????????????????????001000011") - def FMSUB_S = Bits("b???????????????????????001000111") - def FNMSUB_S = Bits("b???????????????????????001001011") - def FNMADD_S = Bits("b???????????????????????001001111") - def FMADD_D = Bits("b???????????????????????011000011") - def FMSUB_D = Bits("b???????????????????????011000111") - def FNMSUB_D = Bits("b???????????????????????011001011") - def FNMADD_D = Bits("b???????????????????????011001111") + def JAL = Bits("b?????????????????????????1100111") + def JALR = Bits("b?????????????????000?????1101111") + def BEQ = Bits("b?????????????????000?????1100011") + def BNE = Bits("b?????????????????001?????1100011") + def BLT = Bits("b?????????????????100?????1100011") + def BGE = Bits("b?????????????????101?????1100011") + def BLTU = Bits("b?????????????????110?????1100011") + def BGEU = Bits("b?????????????????111?????1100011") + def LUI = Bits("b?????????????????????????0110111") + def AUIPC = Bits("b?????????????????????????0010111") + def ADDI = Bits("b?????????????????000?????0010011") + def SLLI = Bits("b010000???????????001?????0010011") + def SLTI = Bits("b?????????????????010?????0010011") + def SLTIU = Bits("b?????????????????011?????0010011") + def XORI = Bits("b?????????????????100?????0010011") + def SRLI = Bits("b000000???????????101?????0010011") + def SRAI = Bits("b010000???????????101?????0010011") + def ORI = Bits("b?????????????????110?????0010011") + def ANDI = Bits("b?????????????????111?????0010011") + def ADD = Bits("b0000000??????????000?????0110011") + def SUB = Bits("b0100000??????????000?????0110011") + def SLL = Bits("b0000000??????????001?????0110011") + def SLT = Bits("b0000000??????????010?????0110011") + def SLTU = Bits("b0000000??????????011?????0110011") + def XOR = Bits("b0000000??????????100?????0110011") + def SRL = Bits("b0000000??????????101?????0110011") + def SRA = Bits("b0100000??????????101?????0110011") + def OR = Bits("b0000000??????????110?????0110011") + def AND = Bits("b0000000??????????111?????0110011") + def MUL = Bits("b0000001??????????000?????0110011") + def MULH = Bits("b0000001??????????001?????0110011") + def MULHSU = Bits("b0000001??????????010?????0110011") + def MULHU = Bits("b0000001??????????011?????0110011") + def DIV = Bits("b0000001??????????100?????0110011") + def DIVU = Bits("b0000001??????????101?????0110011") + def REM = Bits("b0000001??????????110?????0110011") + def REMU = Bits("b0000001??????????111?????0110011") + def ADDIW = Bits("b?????????????????000?????0011011") + def SLLIW = Bits("b0100000??????????001?????0011011") + def SRLIW = Bits("b0000000??????????101?????0011011") + def SRAIW = Bits("b0100000??????????101?????0011011") + def ADDW = Bits("b0000000??????????000?????0111011") + def SUBW = Bits("b0100000??????????000?????0111011") + def SLLW = Bits("b0000000??????????001?????0111011") + def SRLW = Bits("b0000000??????????101?????0111011") + def SRAW = Bits("b0100000??????????101?????0111011") + def MULW = Bits("b0000001??????????000?????0111011") + def DIVW = Bits("b0000001??????????100?????0111011") + def DIVUW = Bits("b0000001??????????101?????0111011") + def REMW = Bits("b0000001??????????110?????0111011") + def REMUW = Bits("b0000001??????????111?????0111011") + def LB = Bits("b?????????????????000?????0000011") + def LH = Bits("b?????????????????001?????0000011") + def LW = Bits("b?????????????????010?????0000011") + def LD = Bits("b?????????????????011?????0000011") + def LBU = Bits("b?????????????????100?????0000011") + def LHU = Bits("b?????????????????101?????0000011") + def LWU = Bits("b?????????????????110?????0000011") + def SB = Bits("b?????????????????000?????0100011") + def SH = Bits("b?????????????????001?????0100011") + def SW = Bits("b?????????????????010?????0100011") + def SD = Bits("b?????????????????011?????0100011") + def AMOADD_W = Bits("b00000????????????010?????0101111") + def AMOXOR_W = Bits("b00100????????????010?????0101111") + def AMOOR_W = Bits("b01000????????????010?????0101111") + def AMOAND_W = Bits("b01100????????????010?????0101111") + def AMOMIN_W = Bits("b10000????????????010?????0101111") + def AMOMAX_W = Bits("b10100????????????010?????0101111") + def AMOMINU_W = Bits("b11000????????????010?????0101111") + def AMOMAXU_W = Bits("b11100????????????010?????0101111") + def AMOSWAP_W = Bits("b00001????????????010?????0101111") + def LR_W = Bits("b00010??00000?????010?????0101111") + def SC_W = Bits("b00011????????????010?????0101111") + def AMOADD_D = Bits("b00000????????????011?????0101111") + def AMOXOR_D = Bits("b00100????????????011?????0101111") + def AMOOR_D = Bits("b01000????????????011?????0101111") + def AMOAND_D = Bits("b01100????????????011?????0101111") + def AMOMIN_D = Bits("b10000????????????011?????0101111") + def AMOMAX_D = Bits("b10100????????????011?????0101111") + def AMOMINU_D = Bits("b11000????????????011?????0101111") + def AMOMAXU_D = Bits("b11100????????????011?????0101111") + def AMOSWAP_D = Bits("b00001????????????011?????0101111") + def LR_D = Bits("b00010??00000?????011?????0101111") + def SC_D = Bits("b00011????????????011?????0101111") + def FENCE = Bits("b?????????????????000?????0001111") + def FENCE_I = Bits("b?????????????????001?????0001111") + def SYSCALL = Bits("b00000000000000000000000001110111") + def BREAK = Bits("b00000000000000000001000001110111") + def RDCYCLE = Bits("b00000000000000000100?????1110111") + def RDTIME = Bits("b00000010000000000100?????1110111") + def RDINSTRET = Bits("b00000100000000000100?????1110111") + def MTPCR = Bits("b0000000??????????000?????1110011") + def MFPCR = Bits("b000000000000?????001?????1110011") + def SETPCR = Bits("b?????????????????010?????1110011") + def CLEARPCR = Bits("b?????????????????011?????1110011") + def ERET = Bits("b00000000000000000100000001110011") + def FADD_S = Bits("b0000000??????????????????1010011") + def FSUB_S = Bits("b0000100??????????????????1010011") + def FMUL_S = Bits("b0001000??????????????????1010011") + def FDIV_S = Bits("b0001100??????????????????1010011") + def FSQRT_S = Bits("b001000000000?????????????1010011") + def FSGNJ_S = Bits("b0010100??????????000?????1010011") + def FSGNJN_S = Bits("b0011000??????????000?????1010011") + def FSGNJX_S = Bits("b0011100??????????000?????1010011") + def FADD_D = Bits("b0000001??????????????????1010011") + def FSUB_D = Bits("b0000101??????????????????1010011") + def FMUL_D = Bits("b0001001??????????????????1010011") + def FDIV_D = Bits("b0001101??????????????????1010011") + def FSQRT_D = Bits("b001000100000?????????????1010011") + def FSGNJ_D = Bits("b0010101??????????000?????1010011") + def FSGNJN_D = Bits("b0011001??????????000?????1010011") + def FSGNJX_D = Bits("b0011101??????????000?????1010011") + def FCVT_L_S = Bits("b010000000000?????????????1010011") + def FCVT_LU_S = Bits("b010010000000?????????????1010011") + def FCVT_W_S = Bits("b010100000000?????????????1010011") + def FCVT_WU_S = Bits("b010110000000?????????????1010011") + def FCVT_L_D = Bits("b010000100000?????????????1010011") + def FCVT_LU_D = Bits("b010010100000?????????????1010011") + def FCVT_W_D = Bits("b010100100000?????????????1010011") + def FCVT_WU_D = Bits("b010110100000?????????????1010011") + def FCVT_S_L = Bits("b011000000000?????????????1010011") + def FCVT_S_LU = Bits("b011010000000?????????????1010011") + def FCVT_S_W = Bits("b011100000000?????????????1010011") + def FCVT_S_WU = Bits("b011110000000?????????????1010011") + def FCVT_D_L = Bits("b011000100000?????????????1010011") + def FCVT_D_LU = Bits("b011010100000?????????????1010011") + def FCVT_D_W = Bits("b011100100000?????????????1010011") + def FCVT_D_WU = Bits("b011110100000?????????????1010011") + def FCVT_S_D = Bits("b100010000000?????????????1010011") + def FCVT_D_S = Bits("b100000100000?????????????1010011") + def FEQ_S = Bits("b1010100??????????000?????1010011") + def FLT_S = Bits("b1011000??????????000?????1010011") + def FLE_S = Bits("b1011100??????????000?????1010011") + def FEQ_D = Bits("b1010101??????????000?????1010011") + def FLT_D = Bits("b1011001??????????000?????1010011") + def FLE_D = Bits("b1011101??????????000?????1010011") + def FMIN_S = Bits("b1100000??????????000?????1010011") + def FMAX_S = Bits("b1100100??????????000?????1010011") + def FMIN_D = Bits("b1100001??????????000?????1010011") + def FMAX_D = Bits("b1100101??????????000?????1010011") + def FMV_X_S = Bits("b111000000000?????000?????1010011") + def FMV_X_D = Bits("b111000100000?????000?????1010011") + def FRSR = Bits("b11101000000000000000?????1010011") + def FMV_S_X = Bits("b111100000000?????000?????1010011") + def FMV_D_X = Bits("b111100100000?????000?????1010011") + def FSSR = Bits("b111110000000?????000?????1010011") + def FLW = Bits("b?????????????????010?????0000111") + def FLD = Bits("b?????????????????011?????0000111") + def FSW = Bits("b?????????????????010?????0100111") + def FSD = Bits("b?????????????????011?????0100111") + def FMADD_S = Bits("b?????00??????????????????1000011") + def FMSUB_S = Bits("b?????00??????????????????1000111") + def FNMSUB_S = Bits("b?????00??????????????????1001011") + def FNMADD_S = Bits("b?????00??????????????????1001111") + def FMADD_D = Bits("b?????01??????????????????1000011") + def FMSUB_D = Bits("b?????01??????????????????1000111") + def FNMSUB_D = Bits("b?????01??????????????????1001011") + def FNMADD_D = Bits("b?????01??????????????????1001111") /* Automatically generated by parse-opcodes */ - def CUSTOM0 = Bits("b??????????????????????0000001011") - def CUSTOM0_RS1 = Bits("b??????????????????????0100001011") - def CUSTOM0_RS1_RS2 = Bits("b??????????????????????0110001011") - def CUSTOM0_RD = Bits("b??????????????????????1000001011") - def CUSTOM0_RD_RS1 = Bits("b??????????????????????1100001011") - def CUSTOM0_RD_RS1_RS2 = Bits("b??????????????????????1110001011") - def CUSTOM1 = Bits("b??????????????????????0000001111") - def CUSTOM1_RS1 = Bits("b??????????????????????0100001111") - def CUSTOM1_RS1_RS2 = Bits("b??????????????????????0110001111") - def CUSTOM1_RD = Bits("b??????????????????????1000001111") - def CUSTOM1_RD_RS1 = Bits("b??????????????????????1100001111") - def CUSTOM1_RD_RS1_RS2 = Bits("b??????????????????????1110001111") - def CUSTOM2 = Bits("b??????????????????????0001010111") - def CUSTOM2_RS1 = Bits("b??????????????????????0101010111") - def CUSTOM2_RS1_RS2 = Bits("b??????????????????????0111010111") - def CUSTOM2_RD = Bits("b??????????????????????1001010111") - def CUSTOM2_RD_RS1 = Bits("b??????????????????????1101010111") - def CUSTOM2_RD_RS1_RS2 = Bits("b??????????????????????1111010111") - def CUSTOM3 = Bits("b??????????????????????0001111011") - def CUSTOM3_RS1 = Bits("b??????????????????????0101111011") - def CUSTOM3_RS1_RS2 = Bits("b??????????????????????0111111011") - def CUSTOM3_RD = Bits("b??????????????????????1001111011") - def CUSTOM3_RD_RS1 = Bits("b??????????????????????1101111011") - def CUSTOM3_RD_RS1_RS2 = Bits("b??????????????????????1111111011") + def CUSTOM0 = Bits("b?????????????????000?????0001011") + def CUSTOM0_RS1 = Bits("b?????????????????010?????0001011") + def CUSTOM0_RS1_RS2 = Bits("b?????????????????011?????0001011") + def CUSTOM0_RD = Bits("b?????????????????100?????0001011") + def CUSTOM0_RD_RS1 = Bits("b?????????????????110?????0001011") + def CUSTOM0_RD_RS1_RS2 = Bits("b?????????????????111?????0001011") + def CUSTOM1 = Bits("b?????????????????000?????0101011") + def CUSTOM1_RS1 = Bits("b?????????????????010?????0101011") + def CUSTOM1_RS1_RS2 = Bits("b?????????????????011?????0101011") + def CUSTOM1_RD = Bits("b?????????????????100?????0101011") + def CUSTOM1_RD_RS1 = Bits("b?????????????????110?????0101011") + def CUSTOM1_RD_RS1_RS2 = Bits("b?????????????????111?????0101011") + def CUSTOM2 = Bits("b?????????????????000?????1011011") + def CUSTOM2_RS1 = Bits("b?????????????????010?????1011011") + def CUSTOM2_RS1_RS2 = Bits("b?????????????????011?????1011011") + def CUSTOM2_RD = Bits("b?????????????????100?????1011011") + def CUSTOM2_RD_RS1 = Bits("b?????????????????110?????1011011") + def CUSTOM2_RD_RS1_RS2 = Bits("b?????????????????111?????1011011") + def CUSTOM3 = Bits("b?????????????????000?????1111011") + def CUSTOM3_RS1 = Bits("b?????????????????010?????1111011") + def CUSTOM3_RS1_RS2 = Bits("b?????????????????011?????1111011") + def CUSTOM3_RD = Bits("b?????????????????100?????1111011") + def CUSTOM3_RD_RS1 = Bits("b?????????????????110?????1111011") + def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011") }