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tile: BaseTile refactor, pt 1

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* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
This commit is contained in:
Henry Cook
2017-12-20 17:18:38 -08:00
parent ba6dd160a3
commit 1cd018546c
18 changed files with 210 additions and 189 deletions
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2
src/main/scala/tilelink/SRAM.scala
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@ -20,7 +20,7 @@ class TLRAM(
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(address) ++ errors,
resources = resources,
resources = device.reg("mem"),
regionType = if (cacheable) RegionType.UNCACHED else RegionType.UNCACHEABLE,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),